Applying innovative FanFET technology to 3D-NAND Flash

Article By : Morgan Chen-Chih Wang

This article introduces the innovative Fan type Field Effect Transistor (FanFET) technology applied to 3D-NAND Flash flash memory and a simple concept that extends to circuits of digital logic...

Imagine the future of high-speed and massive information flow and computation flow, no matter where you are, your mobile device screen (NOR+OLED) will search and explore powerful logical operations and intelligent analysis (NAND, CPU/AI) on the cloud (DRAM) in real time and quickly obtain new information and make decisions. Covering smart homes, automatic transportation, mobile execution, and big data analysis in various fields, high-speed and high-capacity memory and CPU/AI chips will play two major roles in the era of wireless communication and smart computing.

This article will describe the technology, benchmark and highlights of an innovative Fan type Field Effect Transistor (FanFET) applied to 3D-NAND Flash flash memory and a simple concept that extends to circuits of digital logic.

The Roadmap for the Evolution of Transistors

Figure 1 is a technical roadmap showing the current evolution of mainstream transistors and product applications. From the perspective of CMOS technology, in addition to general logic and power device products, there is also NOR flash technology.  For DRAM, NAND, and logic products below 25nm, their transistors have evolved into Surrounding Gate Transistor (SGT), Gate-all-around (GAA, GAAFET), and Fin type Field Effect Transistor (FinFET), respectively.

For example, NAND Flash below 1xnm (strictly speaking, 3D-NAND Flash) is composed of vertical current GAA memory in series; and the logic circuit of FinFET has gradually evolved from CMOS to a two-dimensional enhanced structure, paralleled to multi-fins (multi-fins) or nano-sheets (such as MBCFET) to increase the size of the current.  The above technologies require deep ultraviolet (DUV) or even extreme ultraviolet (EUV) lithographic equipment to complete the corresponding nano-pattern.

Nevertheless, the innovative FanFET is an active device which is similar to the fan shape. It has vertical current and corresponding terminal region, meeting the criteria for making three-dimensional stacking and high density memory. Therefore, it is suitable for applications of transistors and memory.

Fig. 1: The Roadmap of the Transistor Node Technology

The New 3D-NAND Flash Creates the New Transistors

GAA cell is currently the mainstream and the only three-dimensional flash memory technology (3D-NAND Flash) of the world’s major memory manufacturers. GAA was adopted a quadrilateral staggered arrangement, divided into GAA CT cell or GAA FG cell according to the combination of thin film materials.  The feature size of GAA cell products is about 4F2 or more. The structure of GAA also fits multi-layer three-dimensional stacking which is the reason why the need of density of three-dimensional flash memory increases rapidly.

The improvement of memory node technology and density depends on two key technologies: emerging materials and innovative structures.  Memory derived from emerging materials, such as FRAM, MRAM, PRAM and RRAM, has already been manufactured and used by a small number of manufacturers.

For the innovative structure, in addition to increasing the memory density, the simplified method and high-compatibility process also meet the future application and popularity of memory.  From the concept of the closest packed cells, Hexas technology considers the layout and connection of the circuits and demands the rationalization of the model of the three-dimensional device and the three-dimensional process integration. When the three-dimensional NAND flash memory is completed, a brand new transistor is also known as the transistor FanFET, an innovative transistor that is totally different from FinFET and GAA.  Figure 2 shows the structure, coordinates and terminals of FanFET.

Fig. 2: Structure, Coordinates and Terminals of FanFET

Both Transistor and Memory: FanFET

FanFET, having the same basic structure as MOST transistors, can be used as transistors and memory. The main difference between MOST and FanFET lies in the location of the terminal, the 3D partial differential equation of drift-diffusion current, the direction of current flow, and the 3D modular manufacturing process. The structure of FanFET, which can be easily completed by ArF/DUV lithographic equipment and the technology of multilayer film stacks, has vertical currents. FanFET memory cell has the hexagonal close packed (HCP), and the feature size is about 2F2, that is, the unit area density of the FanFET memory cell is twice more than that of the GAA memory cell.

3D-NAND Flash Modulated Manufacturing Processes

The key to the 3D-NAND Flash modular process integration is the formation and relative arrangement of memory cells.  Figure 3 is a benchmark of schematic structure of GAA and FanFET on 3D-NAND Flash memory.   Firstly, the front-end on line process (FEOL) starts with  film stacks of a polysilicon and a silicon nitride, followed by the memory cell manufacturing process, the middle-end of line process (MEOL), and the back-end on line process (BEOL).

Fig. 3: Benchmark of 3D NAND Flash Memory Cells

The combination of the thickness, the uniformity of the deposited film, and the number of stacked layers need to be considered in the film stacks of the FEOL process. The issues need to be considered in the following cell process are: the method and steps of the integration of cell formation, the channel region and the physical mechanism of the transistor operation, and the etching issue of the aspect ratio. The last one is the bit line (BL), the word line (WL) of MEOL process, and metal inter-connection of BEOL process, which may cause some key issues, such as the conductive properties of doped polysilicon or metal wire of BL and WL, higher aspect ratio, CD bias of lithographic alignment,  and contamination of metals or particles are the critical issues.

Key Processes and Differences of Memory Cell Modules

Split GAA is derived from GAA (Split GAA is the author’s tentative name). Figure 4 shows the comparison between the three Split GAA and FanFET process modularization.  Observing the main differences of the four memory cells from a bird’s eye view (GAA process is omitted here),   the split GAA cells manufacturing models used by the first three companies above are based on the GAA process. Having been changed into an ellipse-like shape, GAA cell is split to form a Split GAA cell technically.


Fig. 4:  Benchmark of Main Features of  Cell Formation

The general standard manufacturing processes are stacks of thin films, the definition of the active area (AA), the formation of cell array, the completion of the isolation layer, the connection of wiring, and then stacking.

Take Hexas Technology’s FanFET process flow as an example. The steps are the isolation of intra-cells, the recessed cell process integration, and the isolation of inter-cells. This is the gate last process technology.

The Memory Cell Evaluation between Split GAA and FanFET

The four companies above have similarities, including vertical current, process technology with multi-layer stacking, ways of connecting individual wires, bit lines and word lines.  Seemingly similar in appearance, the structure of the Hexas memory’s current operation region is sharply different from the previous three.

In order to carry out the process of the memory cell module, the first three cells must be fixed at a certain value to meet the subsequent process.  The diameter of the cell is the one of the short axis of the Split GAA cell hole, which affects the final density;  however,  FanFET  memory cell module has no such problems in the process integration because the cell shape and feature size of the FanFET memory cell can be freely adjusted according to the needs of developers, and can be effectively changed the density.  The feature size of the above mentioned three companies is about 3.5F2 ~6F2 because the unit cell itself is a closed loop structure, and the isolation layer between the inter-cells and the intra-cell must all comply with the design rule.

In addition, with the sequences and differences of the various processes, such as the gate first and gate last process technology, the series of the isolation layer and the cell, as well as the film residue and CD bias on the process flow may bring about different degrees of marginal effects.

Limitations of Split GAA

Split GAA may have a serious problem, that is, it is a closed loop structure in unit cell, and this structure could limit the size of the unit cell. When the unit cell shrinks, it will face the problem of filling in the dielectric layer film and BL.  At the same time, Split GAA cell will  increase the feature size resulting in a smaller memory density per unit area.   On the contrary, FanFET can freely adjust the shape and the ratio between  the cell and the isolation layer. The key factor is that FanFET is an open recessed cell, regardless of the exposure and the development of lithography and the dielectric film filling-in process.  It can be completed in the existing 12-inch fab of ArF and DUV lithographic equipment, and the node technology of the process can be ranged from 90 nm to less than 10 nm.

FanFET Technical Highlights and Advantages

Hexas Technology’s FanFET has 10 technical highlights. From a technical point of view, the first group is the innovative high-density transistor cell including,

  1. Be a brand new fan-type field effect transistor (FanFET) structure.
  2. Be applicable to both transistors and memory.
  3. Make multi-layer stacked 3D structure and technology.
  4. Increase the memory density per unit area
  5. Possess diversified technologies: in addition to stand-alone memory technology, it can be extended to embedded systems and computing in memory.

The second group is extendable Moore’s law indicating FanFET can be ranged from 90 nm to less than 10 nm in node technology. From a commercial point of view, the highlights include,

  1. Get win-win business model and strategic profitability.
  2. Make process in Silicon compatibility: The process technology is compatible with the current 12-inch fab.
  3. Reduce development costs and increase capacity utilization.
  4. Share patent rights: co-sharing patent pool and establishing relevant technical specifications.
  5. Establish a complete manufacturing supply chain.

To Increase Future Business Opportunities

Hexas Technology’s innovative FanFET 3D-NAND flash memory, which is compatible with the standard MOST structure, and the most efficient development technology,  has a simple and precise unit cell with the smallest feature size 2F2 and the highest density per volume in 3D process.  In the era of mobile communications and artificial intelligence, Hexas Technology hopes to jointly develop with alliances through the win-win business model in order to derive more technical levels and business opportunities, and to further integrate new material technologies so as to open up nano-scale memory applications in the new blue ocean.

Digital Logic Application of FanFET

With the connection between n-type FanFET and p-type FanFET, they can turn into the prototype of the inverter. Figure 5 is a schematic diagram of the FanFET inverter of the basic unit of digital logic.  FanFET can complete the corresponding digital logic functions through simulation and layout having more kinetic energy and imagination space of research and development on the feature size, electrical characteristics, and 3D process technology.  FanFET, like CMOS, is a transistor that can manufacture memory and logic circuits. In the semiconductor industry, FanFET is a rising star of nano-scale innovative structure and has the potential for development of semiconductor technology.

Fig. 5: Schematic Diagram of the FanFET Inverter

– Morgan Chen-Chih Wang is the CEO of Hexas Technology

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