Automated DRC violation correction speeds designs to tapeout

Article By : Jeanne-Tania Sucharitaves & Rehab Ali

If an IP under review is a decomposed SADP design, correcting DRC violations can become a complex and lengthy process. Automated correction tools can help.

No matter how careful chip design engineers are, and regardless of what implementation tools they use, a verification team will always encounter design rule checking (DRC) errors during the signoff verification of decomposed self-aligned double patterning (SADP) designs. If the design was manually decomposed, the engineer must figure out what modifications are needed, then make changes in potentially multiple decomposition layers to resolve the errors. If a design implementation tool was used to automatically generate the decomposed layout, the correction process typically requires an engineer to make manual changes to the target metal shapes, then re-run the decomposition process to determine if the error is fixed (without introducing any new errors). Both approaches are iterative and time-consuming, which adds to the product costs and extends time to market.

Working together to develop EDA tools to speed this process, GlobalFoundries and Mentor (a Siemens Business) discovered tool functionality that can automatically decompose a layout, or modify an existing partially or fully decomposed layout, while using built-in sign-off DRC rule awareness and error visualization to fix existing DRC errors and avoid creating new ones. The key to auto-fixing DRC errors in SADP designs is to enable the tool to make minor changes in the decomposition that only slightly change the metal shapes (as compared to the originally-drawn target metal shapes) formed on the wafer. The critical factor is to ensure that none of these physical changes affects the layout vs. schematic (LVS) connectivity of the design, or moves any via connections to the metal, to avoid creating functional or resistance changes in the circuit. The only effect is to extend the line ends of some metal lines, which has a minimal capacitive impact on the circuit.

Changes to the on-wafer metal shapes are created by modifying the cut masks generated during the decomposition. These cut modifications occur in three forms: cut sliding, cut merging, and cut dropping.

Cut sliding
To decompose a set of target metal shapes using fill/cut SADP, you place a cut at the tip of every target metal shape line end. These cuts split the tracks into segments—either active target metal or dummy metal. In our experiments with real designs, we found that strictly adhering to the as-drawn target shapes when determining the placement of the cuts can create many types of DRC violations.

Figure 1 demonstrates four different types of DRC violations that might occur when the cuts are placed at the line ends of the target metal shapes:

  • Spacing violations between mandrel cuts occur when two mandrel cuts are too close together to be printed on the same mask.
  • Spacing violations between non-mandrel cuts occur when two non-mandrel cuts are too close together to be printed on the same mask.
  • Spacing violations between a cut and a via occur because trimming the line that close to the via would not meet the requirement for the minimum metal line-end extension beyond the via.
  • Minimum area violations occur when trimming a track into a short segment between the two cuts creates a segment of metal that does not meet the minimum area requirements.

In this process, there are two types of cuts—one that selectively cuts the mandrel tracks, and one that selectively cuts the non-mandrel tracks. Because these two cut types are selective to a particular track type, they do not have spacing constraints between each other. However, each cut type does have spacing constraints within itself.

Figure 1 DRC rule violations caused by line-end cuts

You might ask, “Why would the design implementation tool create target metal shapes, or let you create target metal shapes, that would lead to these violations when decomposed?” The answer is essentially the age-old answer to the more general question of “Why would a design implementation tool create any layout, or let you create any layout, that fails the sign-off DRC checks?” Design implementation is an incredibly difficult process, and the likelihood of producing a layout that is DRC-clean against the sign-off deck the first time out of the implementation tool nearly non-existent. That is why sign-off DRC exists, and why it is so important.

The concept of cut sliding is to shift the placement of one or more of these cuts away from the line ends to resolve DRC violations. The technical challenge for building such functionality is that moving a cut changes the interactions with all the other cuts. The designer’s challenge is to find an optimized placement of interacting sets of cuts that resolves as many errors as possible, while also attempting to minimize the changes to the line-end extensions.

Figure 2 shows how cut sliding can be used to avoid the DRC errors caused by line-end cuts. Several of the cuts have been shifted from their original line-end placement. Shifting the cut away from the edge of the target metal shape has the effect of extending the target metal line when manufactured on the wafer. Notice that the vias are not moved, so the electrical connectivity and path lengths do not change [8]. The benefit of these moved cut placements is that now all four of the original DRC violations have been eliminated.

Figure 2 DRC rule violations caused by line-end cuts can be auto-fixed using cut sliding.

[Continue reading on EDN US: Cut merging also avoids DRC violations]

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