Boosting ADC speed and power by optimizing capacitance

Article By : Don Dingee

Here is a sneak peek at the university research projects aimed at capturing speed and power in analog-to-digital converters.

What’s so hard about making fast analog-to-digital converters (ADCs)? In the digital domain, reducing geometry and upping clock speed usually boost performance. But in the analog realm, smaller transistors and faster clocking may not hold the answers. Along with commercial research on giga sample per second (GSPS) ADCs, research projects in universities are working on optimizing designs and taming an old nemesis, capacitor. These findings are helping both ADC speed and power consumption and enabling even more power savings at lower speeds.

Three architectures have come to the fore, mostly replacing fast but complex, power hungry and hard to calibrate flash converters. Efforts are focusing on the successive approximation register (SAR) ADC and the delta-sigma ADC, or their hybrid, the zoom ADC. In vastly oversimplified terms, these all use a digital-to-analog converter (DAC) output compared with the incoming analog sample, with various loop-filtering and correction techniques, taking the result reached after several comparison cycles; starting at N+1, with N the desired bits of resolution.

Capacitors, the old nemesis mentioned above, often pose a love-hate relationship for most analog engineers. Too little capacitance, signals ring and power rails chatter. Too much capacitance slows down signals like mud. And getting things just right is tough. Matching capacitors is difficult, and parasitic capacitance shows up in inconvenient places, especially when geometries shrink. Capacitors can also be bad news for ultra-low power circuits, drawing charge currents as voltages fluctuate.

To get a sense of what’s going on, here is a sneak peek at a few pieces of research published since 2020; apologies in advance to other teams out there also working on ADC improvements.

Targeting SAR DAC capacitive array

A good summary of issues facing ADC designers is in a 2020 dissertation published by Siyu Tan at Lund University in Sweden. Siyu created designs showing different approaches. Key findings came from 10-bit synchronous SAR (SSAR) and asynchronous SAR (ASAR) designs using 7x time-interleaving, implemented in a 22-nm FD-SOI CMOS process.

The DAC in these designs replaces the conventional binary-weighted N-bit capacitor with a split-capacitor array plus a bridge capacitor, cutting overall capacitance in half. Optimizing the bottom plate sampling reduces charging power by over 93%. This carves out room for redundancy bits, helping settling time and offsetting non-linearity. The ASAR ADC simulates out at 1.4 GSPS, with big power savings on the capacitive array and the simplified clock buffering.

Figure 1 The binary-weighted array shows bottom plate sampling (a), versus split-capacitor array (b) for sub-DAC and main DAC. Source: “High-Speed Analog-to-Digital Converters in CMOS,” Lund University, 2020

Behind an IEEE paywall lurks details of an even bigger leap published in May 2021. A bigger team at Brigham Young University created an 8-bit, 10 GSPS, 8x time interleaved SAR which looks like an ASAR architecture with similar power savings in clock buffering. One of the principal researchers, Eric Swindlehurst, works at Cypress Semiconductor, now part of Infineon. The results after three years of design and another year of test: an ADC consuming only 21 mW at 10 GSPS implemented in a 28nm CMOS process.

The team went full force after the capacitor array, grouping capacitors symmetrically while scaling plate area and spacing to eliminate two-thirds of the bottom plate parasitic capacitance. Redundancy bits also helped their design with quantized sub-radix-2 scaling. They also went after a dual-path bootstrapped switch configuration separating signal from parasitic capacitance, cleaning up non-linearity and improving spurious-free dynamic range by more than 5 dB.

Hunting down more capacitors in the loop

In a different direction, a team at Delft University in the Netherlands went to work on an energy efficient, high linearity, high dynamic range continuous-time zoom audio ADC. Speeds are obviously lower when dealing with audio, but in a mobile device, power consumption is critical. Once again, the key observation is a switched-capacitor front-end used in many designs chewing up power.

The team at Delft University combined an asynchronous 5-bit SAR ADC with a 3rd order single-bit continuous-time delta-sigma modulator. They took a deep dive into the feed-forward loop filter, balancing factors of power consumption, noise, and linearity. In three integration stages, they reduced integration capacitance and added series resistance, making the input look resistive. They also went inside each integration amplifier, adding a chopper to reduce 1/f noise and similarly shifting impedance toward resistive.

Figure 2 The simplified CT zoom ADC with series resistance has added around integration stages. Source: “A Continuous-Time Zoom ADC for Low Power Audio Applications,” Delft University

Implemented in a 160-nm process, this design achieves a 108.1 dB peak SNR, 106.4 dB peak SNDR, and 108.5 dB dynamic range in a 20 kHz bandwidth, consuming only 618 uW.

Little things mean a lot

These three examples share a theme: instead of creating novel ADC architectures, the focus is on optimizing placed and parasitic capacitance for speed and power consumption. Some of the work is being done on 22-nm nodes, a shift for normally conservative analog designs. It will be interesting to see how this research shows up in commercial designs, and if foundries will provide help for analog teams in capturing these small but important optimizations.

This article was originally published on Planet Analog.

After spending a decade in missile guidance systems at General Dynamics, Don Dingee became an evangelist for VMEbus and single-board computer technology at Motorola. He writes about sensors, ADCs/DACs, and signal processing for Planet Analog.


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