Cache partitioning enables RTOS safety-critical response

Article By : DDC-I

SafeMC’s patented cache partitioning and memory pools facilitate a fine-grained layout of physical RAM that minimises cache effects.

DDC-I has released a technology for its Deos safety critical RTOS on multicore processors. The SafeMC technology enables developers to achieve multiprocessor performance without compromising safety-critical task response and guaranteed execution times.

Today’s multicore CPUs are designed to optimise average-case execution times, which maximises overall system throughput. However, these optimisations often come at the expense of worst-case execution time. In a multicore system, contention for shared resources such as L2 cache and the memory subsystem increases not only worst-case execution time, but also the spread between average and worst-case execution. Unfortunately, safety-critical developers must budget for worst-case outcomes, even though those outcomes may be rare. The net result is tremendous underutilisation of CPU performance, as the CPU time budgeted for worst-case scenarios generally goes to waste. The SafeMC technology allows system developers to minimise the effects of the multicore processor hardware through its safe scheduling and advanced partitioning capabilities.

“The worst-case response and guaranteed execution time requirements of safety-critical applications make it very difficult for developers to take advantage of the performance potential of today’s multicore processors unless the underlying operating system has multicore specific enabling technology,” said Greg Rose, vice president of marketing and product management at DDC-I.

SafeMC technology enables developers to manage the execution of tasks and the configuration of multiprocessor hardware in a way that makes it easy to isolate detrimental sources of multicore contention and alleviate multicore bottlenecks. The result is enhanced determinism and increased CPU utilization for safety-critical applications spanning one or more cores.

SafeMC’s patented cache partitioning and memory pools facilitate a fine-grained layout of physical RAM that minimises cache effects on safety critical task execution times. With memory pools, developers can allocate RAM to specific processes or groups of processes. This ensures that all RAM allocated to a given process uses the same collection of cache sets, and that those sets are independent of the cache sets used by other processes, thereby eliminating cache interference between processes on the same or multiple cores.

SafeMC’s multicore scheduling enables developers to minimise the non-deterministic interference that can occur between arbitrary sets of processes executing concurrently on multiple cores. It also allows system integrators to choose optimal scheduling algorithms (i.e., ARINC 653, POSIX, or Rate Monotonic Scheduling) in user specified time slices for groups of processes executing on multiple cores. Developers can allocate processes and process groups across one or more cores, and specify the associated scheduling algorithm and execution time window for each process and group, all to limit interference effects among tasks.

SafeMC also extends DDC-I’s patented slack scheduling technology to multiple cores. Slack scheduling takes advantage of the fact that the average thread execution time is typically much shorter than the worst-case execution time. For those threads where the actual execution time is less than worst-case budgeted time, Deos reclaims the unused time and makes it available to other slack-enabled threads, thereby boosting overall system performance.

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