Cadence's Xcelium Apps enable automotive, mobile and hyperscale design teams to achieve the highest verification performance.
Cadence Design Systems Inc. has launched Xcelium Apps, a portfolio of domain-specific technologies implemented natively on the Cadence Xcelium Logic Simulator kernel that enable automotive, mobile and hyperscale design teams to achieve the highest verification performance. By mixing and matching Xcelium Apps, customers can achieve up to a 10X regression throughput improvement.
The Xcelium Apps portfolio includes the Xcelium Machine Learning (ML) App, which utilizes proprietary ML technology to reduce regression times by learning from previous regression runs and guiding the Xcelium randomization kernel to either achieve the same coverage with significantly less simulation cycles or catch more bugs around specific coverage points of interest. It also features the Xcelium Digital Mixed-Signal (DMS) App, which enables native co-simulation with Cadence Spectre SPICE analog simulation, as well as advanced SystemVerilog real number model-based simulation.
The Xcelium Multi-Core (MC) App, meanwhile, significantly reduces runtime for long-running high-activity tests by multi-threading the Xcelium kernel, such as on gate-level design for test (DFT) simulations. The Xcelium Safety App enables serial and concurrent fault simulation, which when combined with the Cadence safety verification full flow comprised of Jasper Safety, vManager Safety, and Midas Safety Planner, enables the highest performance safety campaign execution for ISO 26262 compliance.
The Xcelium PowerPlayback App enables the massively parallel Xcelium replay of waveforms captured by Palladium emulation onto a timing-annotated gate-level netlist for glitch-accurate power estimation of multi-billion gate SoC designs, while the Xcelium X-Pessimism Removal (XPR) App shortens debug time by using advanced algorithms to make the propagation of “X” values in simulation more accurate.
“Xcelium Apps are the next step in the evolution of logic simulation performance,” said Paul Cunningham, senior vice president and general manager of the System & Verification Group at Cadence. “These apps deliver domain-specific technologies to enable the highest levels of verification performance at both the IP and full-chip level of modern SoC designs.”
The Xcelium Apps and the Xcelium Logic Simulator are part of the Cadence verification full flow, which includes Palladium Z2 emulation, Protium X2 prototyping, the Jasper Formal Verification Platform, the Helium Virtual and Hybrid Studio, the vManager Verification Management Platform, memory and interface Verification IP (VIP), and System VIP. The Cadence verification full flow is part of the Cadence Intelligent System Design strategy.