Cadence has extended its collaboration with Arm to accelerate mobile device silicon success using its digital and verification tools and the new TCS22.
Cadence Design Systems Inc. has extended its collaboration with Arm to accelerate mobile device silicon success using Cadence digital and verification tools and the new Arm Total Compute Solutions 2022 (TCS22), which includes the Arm Cortex-A715 and Cortex-X3 CPUs and the Arm Mali-G715 and Immortalis-G715 GPUs.
Through the collaboration, Cadence has delivered comprehensive RTL-to-GDS digital flow Rapid Adoption Kits (RAKs) for 5nm and 7nm nodes to help customers achieve optimized power, performance, and area (PPA) goals and improved productivity. In addition, Cadence has validated mobile reference platforms for the Cortex-A715 and Cortex-X3 CPUs and the Mali-G715 and Immortalis-G715 GPUs to jumpstart customer verification flows.
The Cadence integrated digital RTL-to-GDS RAKs that have been optimized for SoC development using the latest Arm TCS22 include the Cadence Cerebrus Intelligent Chip Explorer, Innovus Implementation System, Genus Synthesis Solution, Modus DFT Software Solution, Quantus Extraction Solution, Tempus Timing Signoff Solution and ECO Option, Voltus IC Power Integrity Solution, Conformal Equivalence Checking and Conformal Low Power.
The digital RAKs provide Cortex-A715 and Cortex-X3 CPU and Mali-G715 and Immortalis-G715 GPU users with several key features. For example, the Cadence Cerebrus AI-driven flow optimization enables quick and efficient design-specific closure with reduced engineering effort. Cadence iSpatial technology provides an integrated and predictable implementation flow for the fastest design closure. The RAKs also include an innovative smart hierarchy flow to deliver better turnaround times on large, high-performance CPUs. The digital flow’s integrated Tempus ECO technology for signoff offers accurate, final design closure based on path-based analysis. Finally, the activity-aware power optimization engine incorporated with the Innovus Implementation System and the Genus Synthesis Solution significantly reduces dynamic power consumption, enabling customers to achieve low-power goals.
Cadence Verification Flow for Arm Total Compute Solutions
The verification flow includes the Cadence Xcelium Logic Simulation Platform, Palladium Z1 and Z2 Enterprise Emulation Platforms, Helium Virtual and Hybrid Platforms, Jasper Formal Verification Platform, vManager Planning and Metrics, VIP and System VIP tools and content for Arm-based designs.
The Cadence verification flow enables customers to improve verification throughput and achieve advanced software debug for SoCs containing the Cortex-A715 and Cortex-X3 CPUs and Mali-G715 and Immortalis-G715 GPUs. Furthermore, the virtual and hybrid platform reference designs include the Arm Fast Models to enable early software development and verification using the Cadence Helium and the Palladium and Protium platforms, also known as the dynamic duo.
“With the delivery of Arm TCS22, we’re enabling customers to create high-performance, high-efficiency and secure products that provide an optimal user experience across a variety of mobile applications,” said Paul Williamson, vice president and general manager, Client Line of Business, Arm. “By continuing to collaborate with Cadence, our mutual customers can leverage our latest Armv9 CPUs and the Mali-G715 and Immortalis-G715 GPUs alongside the Cadence digital and verification flows to deliver SoCs to market faster.”
“This latest collaboration with Arm further demonstrates our commitment to empowering designers to create the world’s most advanced mobile designs that provide the best user experience,” said Dr. Chin-Chi Teng, senior vice president and general manager, Digital & Signoff Group at Cadence. “Arm has utilized the latest Cadence digital and verification flow innovations to develop Arm TCS22, and we’re jointly enabling customers to leverage these latest innovations to realize optimal power and performance results and a faster path to tapeout.”
The Cadence digital flow enables customers to achieve PPA goals, and the verification full flow provides improved verification throughput. Both flows support the Cadence Intelligent System Design strategy, which enables customers to achieve SoC design excellence.