There are a few other issues with high dielectric constant capacitors (Class 2) that need to be addressed.
When Ceramic Capacitors Go Bad – Aging.
Capacitor Aging applies to all Class 2 ceramic capacitors as they are built of ferroelectric materials. C0G types (Class 1) do not exhibit this aging effect, however, they are built out of non-ferroelectric dielectric materials.
All ferroelectric materials age, yes even ferrite-based magnetic parts age, as do the X7R and other high-density capacitor types.
This aging happens whether the part is in use or, just sitting in a bin somewhere. All Class 2 capacitors will lose capacitance over time.
This aging is due to the magnetic dipoles in the structure becoming less random with time, changing the dielectric constant of the material; this is a reversible process. When the capacitor dielectric material is taken to above its Curie temperature of around 125oC, the material becomes random again and the capacitor returns to its original value. This is called reforming or de-aging. After reforming, the aging process starts all over again. Even reflow soldering will probably heat the capacitors enough so that they reform, as noted on the Johanson Technology FAQ page  which states:
“After the soldering process, the capacitors have essentially been De-Aged.”
Although Johanson Technology suggests that if you are purposely going to de-age your capacitors on a board, you subject them to a 150oC soak for 1.5 hours, just to make sure you get all the capacitors to at least the Curie temperature.
The rate of capacitance aging for X7R types is nominally given as 2.5 to 3% per decade-hours of time since reforming (Figure 1).
This means: After manufacturing, the capacitor loses around 3% for every decade-hour since the capacitor material was last at the material’s Curie temperature.
The next most common Class 2 dielectric used in electronics, the X5R is typically given an aging rate of 3 to 7% depending on the manufacturer, although most manufacturers quote the larger 5 to 7% values. This suggests that just specifying a “X5R type” from several different manufacturers and expecting similar results, can lead to very different aging performance.
Figure 1 A typical capacitor aging chart, like the kind that you will find on some manufacturers’ data sheets. The upper curve is for a C0G. It is flat because these types do not exhibit the aging phenomena. The middle curve is for a typical X7R which may age at around -3% per decade-hour. The lower curve is for an X5R which is reported to age at any rate from -3% to -7% per decade-hour depending on which datasheet you look at. It turns out that these sorts of curves are inaccurate when the capacitors are biased, and in circuit.
If the rate of capacitance change for an X7R capacitor type is 3% per decade-hour. The net capacitance loss, compared to the datum point of 10 hours will be:
This aging is the same basic effect as applying DC bias to the capacitor. More DC bias (field strength) causes more of the magnetic dipoles in the material to line up, causing a decrease in the dielectric constant of the material.
What About Other Factors?
It was always assumed that the DC bias change and the aging capacitance changes happened independently and were merely additive.
Recently, however, it has been documented by Vishay  that adding DC bias to an X7R capacitor can increase the aging rate substantially. Vishay calculated that their capacitors have a nonlinear aging rate when biased to 100% of rated voltage and they report that some of their competitors may have an even greater rate of aging under DC bias (Figure 2).
Figure 2 Vishay’s study of X7R aging when 100% rated DC bias is included. The upper curve is for a Vishay capacitor and the lower curve(s) are some of the worst performances that they measured. Source: Vishay Vitramon 
Figure 2 shows some results of a 50V capacitor being biased at 100% of the rated working voltage. Vishay in their report also measured some 50V capacitors at 40% bias voltage. There, the aging rate was more linear, but, they report that some capacitors still exhibit substantial aging in the first 1000 hours. See the referenced report  for all the details.
The Vishay article also looked at the aging recovery with the removal of DC bias and found that this de-aged the capacitors at least somewhat and they recovered at least partially from the lost capacitance. Again, the results, according to Vishay, were highly dependent on the manufacturer tested.
The Vishay study did not present any data past 1000 hours.
Now you might well ask: “What about the effect of aging if I have DC bias and the operating temperature at higher than 25oC?”
That is an excellent question, a report published in the Journal of Electroceramics in 2008  also seems to show that for X7R types, the effect of DC bias. And, with increased operating temperature, produces yet again an increased and nonlinear aging rate. However, the good news is that this aging rate seems to settle down in the 10,000- to 100,000-hour range to a maximum loss of about -25% compared to the 10-hour datum.
These nonlinear aging rates show a bottoming out with time, making sense from a material’s perspective. As voltage or time is applied to a Class 2 capacitor, the materials’ magnetic dipoles become less random. But there is a point where all the dipoles are 100% aligned, either through applied voltage or time aging, yet there will still be some capacitance as the material still has some dielectric constant, albeit much reduced.
What you have done by applying DC Bias and/or increasing operating temperature is just to accelerate the aging process.
The Vishay study used the classic 0.1µF, 50V-rated, 0603 size, X7R capacitor for their tests. It is not clear how a newer 2.2µF, 10V-rated, 0603 size, X7R capacitor would perform when similarly tested. These newer, lower-rated voltage, higher capacitance capacitors are what we circuit designers are all using more of, and it seems like more work needs to be done to give us the confidence that we have a handle on what the 10,000- to 100,000-hour capacitance limits might actually be in real-world use cases.
A comparison chart may be built for an X7R capacitor based on available data. Table 1 shows the cumulative effects of DC bias, temperature, and time aging on two capacitors that might be picked for a modern application.
Table 1 Comparison of two X7R, 0603-sized capacitors from manufacturers’ data. Both are assumed to have 5V bias and be operating at 70 Deg C. Even though the initial capacitance was double on one of the parts, the final result at 100,000 hours is much closer. All data is based on manufacturer’s data sheets, 100,000-hour aging is estimated.
The first capacitor is a 1µf, 25V, 0603 size, and the second is a 2.2µf, 10V, 0603 size, both are assumed to be biased at 5V and operated at 70oC. The total aging at 100,000 hours is due to normal aging, plus DC bias, plus operating temperature and is extrapolated to be -25% worst case from references  and . Please note: The key word above is “extrapolated”, as I have no data of my own to back this up.
Even this linear multiplicative adding of terms is misleading as the total cannot be greater than probably an 80% capacitance drop total under any circumstances. This is because when all the magnetic dipoles are 100% lined up, the material will still have some residual dielectric constant. Hence, the situation is more complex than the simple back-of-the-napkin linear calculation that Table 1 shows.
More likely is the situation in Figure 3, which was derived from several manufacturers’ published data on DC bias effects alone. Figure 3 does show what happens to the capacitance of the capacitor when the dielectric material dipole alignment is increased from 0% (totally random) to 100% (totally aligned) which would represent the absolute worst case of DC bias, operating temperature, and aging combined.
Figure 3 A plot was made by studying several manufacturers’ curves of DC bias versus capacitance change and was extrapolated to this curve that shows the likely capacitance change versus a X7R capacitor dielectric material dipole alignment. The 0% is random alignment (left-hand side x-axis), and 100% is when the dipoles are aligned (right-hand side x-axis) showing approximately nearly 80% possible total capacitance loss.
The takeaway from all this for me is:
1) I had severe issues after the “Great Capacitor Shortage” of 2017 in how X7R parts acted when the manufacturers were scrambling to meet orders and substitutions, both known and unknown were made. I found a worse drop in capacitance with DC bias, among other parametric issues between capacitor batches produced before and after the shortage took hold in seemingly identical part numbers.
This makes me leery of trusting decades-old manufacturers’ published information, especially when the technology is changing as rapidly as it is. Even if you do your own reliability studies, you can’t be sure when the next capacitor shortage will change all the formulations again and make it all for naught.
2) The newer information on increased aging rate with DC bias and the elevated operating temperature seems to suggest that at 10 years, the designer might be wise to add another 25% to the expected X7R capacitance drop due to aging + operating temperature + DC bias aging effect. This is in ADDITION to the initial capacitance drop due to tolerance, temperature coefficient, and DC bias alone.
3) This accelerated DC bias + elevated operating temperature capacitance drop suggests that using high temperature, accelerated life testing to at least 1000 hours may help to understand the expected true capacitance change expected for longer expected lifetime products. Note: You can’t go much above 90oC for fear of de-aging the capacitors while you are testing them.
4) Using low rated voltage, high capacitance X7R capacitors running at high working voltage percentages may be problematic for bulk output filtering of a switching power supply, where the capacitance is used to stabilize the control loop, especially if you have to reach a longer operational lifetime. Test to at least 1000 hours at elevated temperatures or use another tried and true capacitor technology like tantalum or aluminum electrolytic for your bulk capacitance needs.
5) Using low rated voltage, high capacitance X7R capacitors running at high working voltage percentages may be fine for low dropout regulators (LDO) output filtering applications. In these applications, a maximum series resistance value, and perhaps some minimum capacitance value might be needed, but at the opposite extremes of these values will usually still provide a stable regulator. Check the regulators’ data sheet to verify.
6) Since X7R is the best of the bunch of all the rest of the Class 2 dielectric capacitors, it seems to strongly suggest that X5R’s be relegated to only high frequency bypassing on multi-megahertz digital circuits where the most important aspect of the capacitor is series inductance rather than any capacitance value. Be sure to see Part I of this article and the notes about piezoelectric effects also.
Bonus – Check Those Data Sheets
I looked at the manufacturers published capacitance versus DC bias data for two common, 0603 size, X7R capacitor types. The first one is the common 0.1µF, 50V that is used everywhere for decoupling (Bonus Figure 1), the second is a high density 1µf, 10V type (Bonus Figure 2).
Bonus Figure 1 A comparison of three manufacturers 0.1µF, 50V, 10%, X7R capacitors capacitance versus DC bias.
Bonus Figure 2 A comparison of three manufacturers 1µF, 10V, 10%, X7R capacitors capacitance versus DC bias.
As can be seen, every manufacturer has a different formulation for their X7R dielectric, and it changes based on the rated capacitor voltage. Keep this in mind when you run into a shortage and pick some other “equivalent” part number, it may not be as equivalent as you think!
 Christopher England, Johanson Dielectrics, “CERAMIC CAPACITOR AGING MADE SIMPLE” https://www.johansondielectrics.com/ceramic-capacitor-aging-made-simple
 Vishay Vitramon, Paul Coppens, Eli Bershadsky, John Rogers, and Brian Ward, “Time-Dependent Capacitance Drift of X7R MLCCs”, Vishay Vitramon, December 2021 https://www.vishay.com/docs/45263/timedepcapdrix7rmlccexptoconstdcbiasvolt.pdf
 Tsurumi, T., Shono, M., Kakemoto, H. et al. “Mechanism of capacitance aging under DC-bias field in X7R-MLCCs”, Journal of Electroceramics, Volume 21, 2008. https://link.springer.com/article/10.1007/s10832-007-9071-0
This article was originally published on EDN.
Steve Hageman has been a confirmed “Analog-Crazy” since about the fifth grade. He has had the pleasure of designing op-amps, switched-mode power supplies, gigahertz-sampling oscilloscopes, lock-in amplifiers, radio receivers, RF circuits up to 50 GHz, and test equipment for digital wireless products. He knows that all modern designs can’t be done with Rs, Ls, and Cs, so he dabbles with programming PCs and embedded systems just enough to get the job done.
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