Here are more PWM ripple-cancellation design ideas.
Several years ago, I published a design idea (See Figure 1: “Cancel PWM DAC ripple with analog subtraction,” November 28, 2017) showing a simple trick for the cancellation of PWM output ripple. It employs passive summation of the usual PWM signal with its AC-coupled inverse, thus dramatically attenuating the undesired AC (ripple) component without affecting the wanted DC component.
Figure 1 Cancel PWM DAC ripple with analog subtraction.
Happily, “Cancel…” was well received generally. It even earned a few pages covering it and some terrific refinements by authors Winfield Hill and Paul Horowitz in the popular “The Art of Electronics: The x-Chapters, 4x.25 Ripple Reduction in PWM,” pp383-385.
One of these TAoE improvements addressed the fact that PWM DAC accuracy tends to be limited by dependence on digital logic power supplies which, as H&H aptly point out, “are notoriously inaccurate.” Their clever fix (see Figure 2) is to add precision analog switches and an accurate voltage reference to the usual PWM topology, thus isolating the DAC output from logic supply inaccuracy. One switch generates a precision version of the usual PWM waveform while the other generates its inverse. Adding the AC-coupled component of the latter to the DC of the former performs the ripple-canceling analog subtraction as described in my 2015 design idea (DI).
Figure 2 Sketch of TAoE PWM accuracy improvement concept
This is of course an elegant, perfectly workable, and effective solution to the PWM accuracy problem.
However, since two analog switch packages are required for each DAC, if multiple channels of PWM DA conversion are needed the package count may become inconveniently large. Also, as the number of channels increases, so does the total loading placed upon Vref, which, depending on the reference device used, may eventually degrade the accuracy of the reference voltage.
A simple variation on Figure 2 is therefore shown in Figure 3, in which the PWM logic control signal is used to derive the ripple-cancellation signal, thus saving an analog switch and cutting by half Vref loading. This requires scaling the R2C2 ripple-subtraction components by a factor X = Vlogic/Vref, which of course will only work as well as X is stable. Note also that the PWM setpoint must be 1’s complemented (V = -V – 1), which is easily done in software.
Figure 3 PWM logic signal used for Ripple Cancellation, thus saving a switch.
In case Vlogic isn’t stable enough for Figure 3 to work, Figure 4 shows yet another different implementation of the TAoE accuracy-promoting concept that utilizes a method of precisely servoing pulse area (amplitude x duration x frequency) to an accurate reference voltage, as shown in another recent DI in the context of VFC analog to digital conversion.
Figure 4 Q2 pulse area servoed to voltage reference.
Figure 4 relies on the ability of adjustable voltage references like the TL431 to act as analog comparators/integrators with accurate built-in thresholds, as shown in Figure 5.
Figure 5 LT431 as precision comparator/difference amplifier with built-in Vref (from LT431 datasheet).
The LT431 (U1) integrates the average difference of U2 pin2 to its internal 2.50V reference and forces equality by increasing Q2 pulse duration when Fclk x pulse duration x 5V = pulse area is less than 2.5V, and decreasing it when greater than 2.5. R1C4 sets the time constant of the integration, R4 provides compensation for U1’s input bias current (~1.8µA), and R5 provides pullup for U1’s output.
U2’s inherent internal device matching (propagation and transition times, etc.) cause the other three bits to accurately track the flip-flop inside U2’s feedback loop, thus providing accurate calibration for all three PWM channels. The associated RC networks implement ripple cancelation, and if all three are populated, provide three accurate DACs from only two device packages.
Of course, if fewer than three channels are needed, not all the ripple cancellation networks need to be populated.
This article was originally published on EDN.