Cancel PWM DAC ripple with analog subtraction—revisited

Article By : Stephen Woodward

Improving upon an old design idea for filtering and attenuating PWM DAC output ripple to yield an increase in respond speed without any increase in circuit complexity and cost.

Once upon a time (2017), I published a simple design idea for filtering and attenuating PWM DAC output ripple that I’d found very useful for over a decade.

It works by passive summation of the PWM signal with its AC-coupled inverse for the purpose of attenuating the unwanted AC ripple signal component without affecting the DC component (Figure 1).

Figure 1 The original ripple subtraction topology.

However, some of the finer details of how the idea works were not fully explored in the original short article. Here’s some of what was omitted.

The circuit’s basic principle of operation is passive summation (via R1 and R2) of the AC coupled (via C2) inverse of the PWM ripple signal current with the PWM signal current, followed by integration of the sum in DAC output capacitor C1. The resultant partial cancellation of ripple components allows adequate ripple attenuation while using a much shorter filter time constant than would otherwise be required for a single-stage RC filter. Faster response and shorter settling times are the payoff.

However, a drawback of this current-mode scheme that limits its speed is that immediately following a step change in the PWM input duty cycle, the R1 and R2 currents will be opposite in sign but equal in magnitude so that their sum must momentarily equal zero. Consequently, with nothing for C1 to integrate, the DAC output signal can’t begin to respond to the step until C2 has begun to charge, reducing the current through R2, making the R1 and R2 currents unequal and giving C1 something besides zero to integrate. This undesirable null interval is shown in Figure 2 as a time delay evident in the rising edge of the output waveform.

This limitation on DAC response time seems to be an unavoidable shortcoming of the current-mode summation topology. While it’s still (much) faster than a single stage RC filter, maybe it’s not as fast as it could/should be.

Figure 2 Current-mode ripple subtraction response showing leading edge delay.

So, I started wondering. What would happen if, instead of currents, ripple and PWM voltages were first computed and then subtracted from each other to achieve ripple cancellation? Could a little more performance be squeezed from the original idea without losing the simplicity that made it attractive in the first place?  Figure 3’s topology was the answer.

Figure 3 New voltage-mode ripple subtraction circuit.

Operation of the new circuit relies on series connected capacitors C1 (which makes the PWM DC voltage component) and C2 (providing the inverted ripple component). Voltage summation is inherent from the series capacitor connection so that, as in the 2017 circuit, AC ripple is subtracted from DC output. It turns out that ripple attenuation adequate for 8 bit resolution happens if the R1C1 time constant is made equal to just 2Tpwm, or twice the PWM period—only 512µs in this example of 8bit PWM with a 1MHz clock. Faster clocks would of course allow even shorter time constants.

Note that the total component count of the new filter circuit is exactly the same as the original:  One inverter (e.g., 1/6 SN74HC04), two resistors, and two capacitors.

Figure 4 shows its step response that now begins immediately at T = 0, unlike the current-mode summation delay of Figure 2, yielding 8bit settling in ~16 PWM cycles = ~4ms for this Tpwm.

Figure 4 Voltage-mode step response showing no leading edge delay.

 Figure 5 compares the 8bit step settling time of the original current-mode design (~23 Tpwm) to the new voltage-mode version (~16 Tpwm).


Figure 5 Comparison of current-mode (red) versus voltage-mode (green) response.

 This 44% (23/16) increase in response speed seems a worthwhile performance improvement, especially given the associated 0% increase in circuit complexity and cost.

Elaborations applied to the original current-mode topology (e.g., utilizing faster clock rates, precision analog switches and voltage references to improve precision, noise, and accuracy) will of course apply directly to this new voltage-mode version.


This article was originally published on EDN.


Leave a comment