Care and feeding of FPGA power supplies

Article By : Nathan Enger

This article will discuss constraining specifications for the Altera Arria 10 FPGA, and what they mean for a power supply design.

Modern FPGAs are among the most complex integrated circuits ever created. They employ the most advanced transistor technology and cutting-edge architectural structures to achieve both incredible flexibility and highest performance. Over time, as technology has advanced, this complexity has dictated certain compromises in the design and implementation of systems using the FPGAs. This is nowhere more apparent than in the power supplies, which must be ever more accurate, more agile, more controllable, smaller, more efficient, and more fault aware with each new FPGA generation.

In this article, we look specifically at some of the constraining specifications for the Altera Arria 10 FPGA, and what they mean for a power supply design. Then we discuss the best power delivery solutions, and lay out the plan to successfully meet all of the specifications and make our FPGA perform at its optimal efficiency, speed, and power level using Analog Devices’ complete set of Power System Management (PSM) ICs, including the LTC3887, LTC2977 and LTM4677.

FPGA power requirements (interpreting the data sheet)
Engineers should spend most of their time programming, and don’t want to spend time and energy thinking about designing suitable power supplies. Indeed, the best approach to power delivery is to use a robust, flexible, proven design that meets the requirements and expands with the project. This frees the engineer for the important work of designing a terabit-per-second encrypted parallel wireless optical orbital Internet platform with background Bitcoin miner, or something similar. Here we take a closer look at some of the important power specifications and what they mean.

Voltage accuracy
Core power supply voltage is one of the most important keys to balancing FPGA power and performance. The specification documents give a range of acceptable voltages, but the total range is not the complete picture. As with all things, there are trade-offs and optimizations to be made.

Table 1 is an example core voltage specification from the popular Altera Arria 10 FPGA1. Though these numbers are specific to the Arria 10, they are representative of other FPGA core voltage requirements. The range amounts to a ±3.3% tolerance around the nominal voltage. The FPGA will operate just fine within this voltage window, but the complete picture is more complicated.

Table 1 Altera Arria 10 Core Voltage Specification

Notice the line labeled “SmartVID”, with a range of 0.82V to 0.93V. This represents a broad range of voltages that are possible when the FPGA is requesting its own core voltage through the SmartVID interface (more on this later). This SmartVID specification is an indication of an underlying truth about the FPGA: it can operate at different voltages, depending upon its particular manufacturing tolerance, and upon the particular logic design that it is implementing. The static voltage required by one FPGA might be different from another FPGA. The power supply must be able to respond and adapt.

The goal is to produce just the right performance level to operate the programmed functions without burning unnecessary power. We know from semiconductor physics, as well as published data from Altera, Xilinx (Figure 1), and others, that both dynamic and static power will increase dramatically with increased core VDD, so the goal is to give the FPGA just enough voltage to meet its timing requirements, but no more. Excess power dissipation does nothing to increase performance. In fact, it makes things worse because transistor leakage current increases with higher temperatures, dissipating even more unwanted power. For these reasons, the imperative is to optimize the voltage for the design and operating point.

Figure 1
Xilinx Virtex V Power vs Core VCC

This optimization process requires a very accurate power supply for success. Regulator inaccuracy must be baked-into the error budget and subtracted from the available voltage range that can be used for optimization. If the core voltage drops below the requirement, the FPGA may fail due to timing errors. If core voltage drifts above the maximum specification it may damage the FPGA, or it may create hold-time failures in the logic. All of these scenarios must be guarded against by taking into account the power supply tolerance range, and only commanding voltages that are guaranteed to remain within the specification limits.

The problem is that most power regulators are not accurate enough. The regulated voltage may be anywhere within the tolerance range around the commanded voltage, and it may drift with load conditions, temperature, and age. A power supply that guarantees a ±2% tolerance may regulate anywhere within a 4% voltage window. In order to compensate for the possibility that the voltage may be 2% too low, the commanded voltage must be raised by 2% above that required to meet timing. If the regulator then drifts to +2% above the commanded voltage it will operate 4% above the minimum voltage required at that operating point. This still meets the specified voltage required by the FPGA, but it wastes a lot of power (Figure 2).

Figure 2
Power supply regulator tolerance trade-offs

The solution is to choose a power supply regulator that can operate with a much tighter voltage tolerance. A regulator with a ±0.5% tolerance can be commanded to operate much closer to the minimum required specification at the desired operating frequency, and it is guaranteed to be less than 1% from that required voltage. The FPGA will be functional, and it will be dissipating the minimum power possible at that operating condition.

The LTC388X family of power supply controllers guarantees regulated output voltage tolerance better than ±0.5% over a wide, configurable voltage range. The LTC297X family of power system managers guarantee a trimmed voltage regulator tolerance of better than ±0.25%. With these accuracies, there is a clear path to optimizing the power vs performance trade-off for any FPGA.

Thermal management
A subtler implication of power supply accuracy manifests itself in thermal budget. Because static power dissipation is far from negligible, the FPGA heats up even when it is doing nothing. The increased temperature causes more static power dissipation, which further increases operating temperature (Figure 3). Adding unnecessary voltage to the power supply only makes this problem worse. As we mentioned, an inaccurate power supply requires a guard band in operating voltage to ensure that there is enough voltage to do the job. The power supply voltage uncertainty that results from variability in tolerance, system assembly variability, and operating temperature can create voltages significantly higher than the minimum required. This additional voltage, when applied to the FPGA, can cause thermal complications, or even thermal run-away at high processing loads.

Figure 3
Power supply current vs operating temperature

The remedy is a very accurate power supply that creates just the right voltage, and no more than necessary, which is exactly what the ADI Power System Management devices do well.

Smart VID2 is the Altera name for the technique of operating each individual FPGA at its optimal voltage, as requested by the FPGA itself. There is a register inside of the FPGA that contains a device-specific voltage (programmed at the factory) at which the FPGA is guaranteed to operate efficiently. A piece of compiled IP inside of the FPGA can read this register and make a request over an external bus to the power supply to provide this exact voltage (Figure 4). Once the voltage is reached, it remains static during operation.

Figure 4
Altera SmartVID structure

The demands of the SmartVID application on the power supply include the specific bus protocol, voltage accuracy, and speed. The bus protocol is one of several methods that the FPGA uses to communicate its required voltage to the power regulator. Of the available methods, PMBus is the most flexible because it addresses the widest variety of power management ICs. The SmartVID IP uses two PMBus commands: VOUT_MODE, and VOUT_COMMAND, with which it commands the PMBus compliant power regulator to the correct voltage.

The voltage accuracy and speed requirements for the regulator include an autonomous boot voltage (before the PMBus is active), the ability to accept a new voltage command every 10ms, the ability to take 10mV steps every 10ms during the voltage adjustment phase, and to settle to within 30mV (~3%) of the target within the 10ms step time, ultimately ramping to the commanded voltage and remaining static during FPGA operation.

Though Altera uses the name SmartVID, there are other similar techniques in use around the industry that accomplish much the same thing. One of the simplest is to test each board at the factory and program into the power supply’s nonvolatile memory an exact voltage that optimizes performance for that particular board. This technique does not require any further intervention for the power supply to operate at the correct voltage. This is an advantage of a power supply manager or controller with EEPROM.

All of the requirements for Altera SmartVID can be met by the LTC388X family of power supply controllers. In addition the LTM4675/LTM4676/LTM4677 µModule regulators easily meet the requirements and offer a complete solution in a single compact form.

Timing closure
The computing speed of any logic block depends on its supply voltage. Within limits, a higher voltage gives faster performance. We have already seen why we cannot simply operate at the highest voltage, thus guaranteeing the best speed. On the other hand, we must operate at a high enough voltage for the application, as shown in Figure 5.

Figure 5
FPGA operating frequency vs VDD trade-off

An important implication of Figure 5 is what can be done when a particular design does not meet its logic timing requirements and falls into the “failing” area. Often the edge between functional and failing is not well defined before a design is committed to hardware, and the particular voltage at which it will pass timing cannot be pre-determined. The only options are to either commit in advance to a voltage that is well above the minimum, thus wasting power to guarantee functionality, or to design a flexible power supply that can adapt to the needs of the hardware at test time, or even, as in the case of SmartVID, at power-up time. The ability to adapt to unknown demands makes the accuracy of ADI PSM devices more valuable, as FPGA designers can trade-off power for performance in the real design, and at any stage of development.

[Continue reading on EDN US: Power supply sequencing 101]

Nathan Enger is a mixed signal applications engineer at Analog Devices.

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