Synopsys' new RF design flow, developed with Ansys and Keysight for the TSMC N6RF process, boosts 5G SoC development productivity.
EDA suppliers joining hands with cloud platforms mark a major shift in IC designs moving beyond enterprise-level toolset licensing models.
Three RTL DUT code examples illustrate the trouble that can occur when comparing the results from simulation and formal side-by-side.
Blindly combining simulations and formal analysis can fool design engineers in believing that they have made a solid progress.
Synopsys and Analog Devices are collaborating to provide model libraries for DC/DC ICs and µModule (micromodule) regulators with Synopsys’ simulation tool Saber.
Like IC design, the EDA and IP industries are an intrinsic part of the IC manufacturing ecosystem spearheaded by semiconductor foundries.
Synopsys' new DesignWare ARC NPX6 NPU IP delivers up to 3,500 TOPS performance for automotive, consumer, and data center chip designs.
Samsung Foundry has achieved high silicon correlation with the jointly developed solution built on Synopsys PrimeTime signoff technology and Ansys RedHawk-SC.
Design verification groups are using formal methods, though not consistently. Here is an insight on their practical advantages in IC design.