2022-01-27 - Nexar

SiliconExpert partners with Nexar to address component lifecycle issues

SiliconExpert is bringing comprehensive part data into the Altium PCB design tool workflows.

2021-12-28 - Manu Kumar and Vaibhav Anand

Understanding the specific use cases for Simulink and Stateflow

While both are capable of modelling and simulating a control algorithm on their own, using each of them for certain tasks brings the best out of these tools.

2021-12-15 - Susan Nordyk

CAD models join PCB design platform

SnapEDA's library of CAD models is now part of Nexar's growing ecosystem of cloud-based PCB design tools.

2021-11-30 - Majeed Ahmad

Profile of a traceability tool promising automation in SoC designs

The tool identifies and fixes traceability gaps between disparate systems like requirements, specs, EDA and software code in SoC designs.

2021-11-26 - Ansys

Realtek and Ansys accelerate complex IC design with advanced simulation workflow

Ansys RaptorH detects and reduces problematic electromagnetic interference and slashes modeling time up to 10x.

2021-11-22 - Deekshith Krishnegowda

A primer on engineering change order (ECO) using Conformal

Here is a detailed treatment of the premask flatten Cadence Conformal ECO flow that is widely used in the semiconductor design industry.

2021-11-18 - Kiran Vittal

Advanced verification: unlocking the door to a new era of AI chips

A look at how chip manufacturers will have to adjust hardware architecture in order to accommodate ever-growing demand for increased AI functionality.

- Stephen Las Marias

Cadence’s X factor

Cadence Sigrity X has been honored with the Best EDA Product of the Year award at the inaugural EE Awards Asia.

2021-10-22 - Mark Waller

What can analog EDA industry learn from word processor

EDA software needs to imbed intelligent decision making into analog design flow to enable engineers to focus on their designs intricacies.

2021-10-06 - Deekshith Krishnegowda, Marvell Technology

A primer on logical equivalence checking (LEC) using Conformal

Logical equivalence check is an important phase in the IC design process where the design is evaluated without providing test cases.