The EDA power integrity solution for the past 20 years has been post-layout SPICE simulation. That must change for bigger analog systems.
As the industry migrates to FinFET technologies, IC layout parasitics has become the dominant source of bottlenecks in mixed-signal SoCs.
DDR is used on many of the interfaces in computer systems, one of which relates to the way the processor interfaces with the memory.
The complexity in clocking subsystems in SoC designs is paving the way for automation to validate multiple combinations of clock signals.
Under the competitive pressures of the semiconductor industry, chip designers are choosing to migrate to cloud computing technologies.
Creating the right floorplan for IoT chips is a critical task that must evolve and be refined as the project progresses.
Mouser Electronics' engineering customers have collectively downloaded more than 1 million models using the ECAD resource on mouser.com.
The new SnapEDA search capability on DesignSpark provides engineers with millions of free CAD models, helping them design electronics faster.
Using FPGAs to verify the SoC design is a powerful tool and is becoming a very important part of semiconductor design.