The SOC2 was designed and taped out in a TSMC 16nm technology by Bar-Ilan University SoC Lab, as part of the HiPer Consortium.
QuickLogic and eTopus' disaggregated eFPGA-enabled chiplet template delivers design flexibility and bandwidth for high performance applications.
Here is how the eFPGA technology is cashing in on the SoC design movement with a matrix of new possibilities for chip designs.
eFPGA has become a significant factor in chip design, particularly as the industry moves to the more complicated and expensive process nodes.
Microchip has launched the second development tool offering in its Smart Embedded Vision initiative for designers using its PolarFire RISC-V SoC FPGA.
The ForgeFPGA Family will address the underserved market need for relatively small amounts of programmable logic.
The eFPGA technology is very generic and works like an off-the-shelf FPGA chip to bring logic reconfigurability to ASIC and SoC devices.
Next-gen space-grade semiconductors will consume almost 100W, but with junction temperatures remaining the same, removing this heat is paramount for reliability and performance.
QuickLogic's low power, multi-core MCUs, FPGAs and embedded FPGAs, and voice and sensor processing devices are now available at the Digi-Key Marketplace.
Tool makers are joining hands with FPGA suppliers like Xilinx to help designers simulate their power systems with accurate and reliable data for specific Xilinx FPGAs.