2016-09-04 - Mufaddal Saifee & Jaymin Patel

Coding consideration for pipeline flip-flops

To achieve better performance, designs nowadays have their data pipelined through chains of flip-flops.

- Mufaddal Saifee, Jaymin Patel

Making a reset usage strategy in ASIC/FPGA designs

The need for reset is governed by the system design and application, and various data and control paths are designed to use a reset signal.

2016-08-23 - Rick Merritt

Intel to churn out Altera’s Stratix 10 by end of 2016

CEO Brian Kraznich promises “no changes in existing or planned products” using ARM cores.