Multi-patterning strategies for navigating the sub-5 nm frontier, part 3
Determine the best self-aligned multi-patterning process solution for your advanced node applications.
Reuse existing verification assets with the Portable Test and Stimulus Standard
How do we shorten our path to the rich rewards that PSS promises?
Machine learning in EDA accelerates the design cycle
IC designs keep growing in complexity, but AI and ML can shrink design cycles.
Macro models let engineers simulate circuits and systems
Mathematical models if circuits and systems give you a head start on developing your products before you're ready to build…
Automate ESD protection verification for complex ICs
Take an in-depth look at full-chip ESD protection verification, and how new automated verification tools and methodologies are helping to…
Formal-based methodology cuts digital design IP verification time
Changing your methods of performing verification can reduce verification time by several weeks.
Getting in sync with UVM sequences
Writing sequences for the SystemVerilog UVM testbench is an essential, but often misunderstood, part of the design verification process.
Get those clock domains in sync
With ICs and boards having many circuits, timing is critical. Multiple clock domains solve some timing problems, but you must…
Multi-patterning strategies for navigating the sub-5 nm frontier, part 1
In this first installment of a practical introduction to advanced multi-pattern semiconductor processes, we'll explore self-aligned double-patterning and self-aligned quadruple-patterning…
Parametric on-chip variation: A step towards accurate timing analysis
To accommodate more functionality on a single chip, the semiconductor industry is shrinking down the transistor technology at every node.…