imec demos backside power delivery with BPRs for back- and frontside routing
The novel routing scheme with decoupled power and signal wiring acts as a scaling booster for future logic technologies (2nm…
Synopsys and Analog Devices collaborate to accelerate power system design
Synopsys and Analog Devices are collaborating to provide model libraries for DC/DC ICs and µModule (micromodule) regulators with Synopsys’ simulation…
TSMC targets conversion to 1.4-nm process node in June
TSMC plans to convert its 3-nm process R&D into a 1.4-nm process in June and thus reclaim sub-2-nm leadership from…
Apple lawsuit puts spotlight on SoC design engineering
Apple's lawsuit claims that Rivos has committed trade secret theft of its homegrown chip designs.
Disrupt or be disrupted: Intel and the great semiconductor fab game
Find out where Intel stands in its bid to compete with fab business behemoths TSMC and Samsung.
A primer on security in the key stages of IC manufacturing lifecycle
Here is how engineers can identify the threats at each step of the IC production lifecycle and subsequently mitigate them.
Deep silicon etch technology enables next-gen power devices
Lam Research's Syndion GP allows chipmakers to develop next-gen power devices and power management ICs using deep silicon etch technology.
Samsung Foundry adopts Synopsys and Ansys co-developed solution for advanced-node, energy-efficient chips
Samsung Foundry has achieved high silicon correlation with the jointly developed solution built on Synopsys PrimeTime signoff technology and Ansys…
Key options for analog debugging on bare-metal systems
Streaming data from firmware and displaying it on an oscilloscope can be a powerful tool and can speed up the…
IC design: A short primer on the formal methods-based verification
Design verification groups are using formal methods, though not consistently. Here is an insight on their practical advantages in IC…