With the rapid deployment of artificial intelligence (AI), the focus of AI system on chip (SoC) design has been on…
Creating and decomposing a DRC-compliant design for self-aligned multi-patterning processes is not a trivial matter.
Functions in an SoC communicating with each other through an interconnect architecture is not so different from a network.
There is a worldwide interest in 2D materials, especially their promise to further extend the logic chip technology roadmap.
As system complexity continues to rise, breakthroughs are needed if EDA is to keep ahead of SoC design challenges.
Here is a chronicle of chip designer Jim Keller’s journey, which spans four semiconductor architectures: x86, PowerPC, MIPS, and Arm.
Re-programming SRAM and flash-based space-grade FPGAs in-orbit offers flexibility to change functionality and improve system performance in response to changing…