Building security into AI SoCs at silicon level
With the rapid deployment of artificial intelligence (AI), the focus of AI system on chip (SoC) design has been on…
Creating and decomposing a DRC-compliant design for SAMP processes
Creating and decomposing a DRC-compliant design for self-aligned multi-patterning processes is not a trivial matter.
NoC technology opens up new architectural options
Functions in an SoC communicating with each other through an interconnect architecture is not so different from a network.
2D materials promise to extend the logic chip technology roadmap
There is a worldwide interest in 2D materials, especially their promise to further extend the logic chip technology roadmap.
EDA breakthroughs needed to conquer evolving SoC design challenges
As system complexity continues to rise, breakthroughs are needed if EDA is to keep ahead of SoC design challenges.
Chip designer Jim Keller’s journey spans 4 semiconductor architectures
Here is a chronicle of chip designer Jim Keller’s journey, which spans four semiconductor architectures: x86, PowerPC, MIPS, and Arm.
CES panel tracks RISC-V’s journey to commercial processors
A panel discussion took a closer look at the RISC-V and processor design areas and how it’s creating a healthy…
Generating track masks for SAMP processes
Learn the decomposition requirements for generating track masks for SAMP processes while complying with all relevant DRC.
AMD acquiring Xilinx to boost data center offerings
AMD is reportedly acquiring FPGA design house Xilinx to boost its server and data center chip offerings.
Space-grade FPGAs can be re-programmed in-orbit
Re-programming SRAM and flash-based space-grade FPGAs in-orbit offers flexibility to change functionality and improve system performance in response to changing…