Single-function analog ICs solve problems without giving headaches
There’s a need for single-function analog ICs to crisply solve specific problems...
Scrubbing SRAM-based FPGAs to prevent the accumulation of SEUs
SRAM-based FPGAs are increasingly being used in-orbit, and if an essential bit is flipped, the consequences could be catastrophic.
GaN switcher ICs boost power output
Additions to the InnoSwitch3-MX series of isolated switchers enable PSU designs with continuous output power of up to 75 W…
Multi-patterning strategies for navigating the sub-5 nm frontier, part 3
Determine the best self-aligned multi-patterning process solution for your advanced node applications.
Reuse existing verification assets with the Portable Test and Stimulus Standard
How do we shorten our path to the rich rewards that PSS promises?
Machine learning in EDA accelerates the design cycle
IC designs keep growing in complexity, but AI and ML can shrink design cycles.
Macro models let engineers simulate circuits and systems
Mathematical models if circuits and systems give you a head start on developing your products before you're ready to build…
Automate ESD protection verification for complex ICs
Take an in-depth look at full-chip ESD protection verification, and how new automated verification tools and methodologies are helping to…
Formal-based methodology cuts digital design IP verification time
Changing your methods of performing verification can reduce verification time by several weeks.
Getting in sync with UVM sequences
Writing sequences for the SystemVerilog UVM testbench is an essential, but often misunderstood, part of the design verification process.