Even novel process enhancements are coming up short in the face of massive gate counts placed side by side with analog circuitry in SoC designs of 16nm and below.
SoC developers must become system developers to properly integrate analog and digital IP in silicon and handle extraordinary complexity and functionality.
Bob Cook had a knack for trouble-shooting semiconductors. Jack Kilby tapped Cook as TI's lead engineer on an early NASA project.
To avoid data loss, designers need to ensure that setup- or hold-time violations don't occur during clock domain crossing.
Using FPGAs to verify the SoC design is a powerful tool and is becoming a very important part of semiconductor design.
Roller-based techniques and tools can now fabricate active electronic components as well as their interconnection.
With the rapid deployment of artificial intelligence (AI), the focus of AI system on chip (SoC) design has been on building smarter, faster and cheaper devices.
Creating and decomposing a DRC-compliant design for self-aligned multi-patterning processes is not a trivial matter.
Functions in an SoC communicating with each other through an interconnect architecture is not so different from a network.
There is a worldwide interest in 2D materials, especially their promise to further extend the logic chip technology roadmap.