The EMI filter resonance can affect conducted emissions, as shown in the design example of parasitics in an EV onboard charger (OBC).
Can China's top fab SMIC mass produce chips at its newly developed 7nm node? The blog attempts to answer this important but tricky question.
TSMC is on track to launch the much-awaited 3nm process node in September, and Apple will be its first 3nm chip manufacturing customer.
A look at using custom extensions in a RISC-V processor to enable power, performance and area optimized true wireless stereo earbuds SoC design.
Automated assembly provides a solid base in SoC designs while allowing differentiation in architectures for memory, power, and security.
Vic Kulkarni of Si2 presents his views on the democratization of chip design following the panel discussion on the subject at DAC 2022.
The electronic system design (ESD) industry revenue increased by 12.1% YoY to $3.54 billion in Q1 2022, according to the ESD Alliance.
The novel routing scheme with decoupled power and signal wiring acts as a scaling booster for future logic technologies (2nm and beyond).
Synopsys and Analog Devices are collaborating to provide model libraries for DC/DC ICs and µModule (micromodule) regulators with Synopsys’ simulation tool Saber.
TSMC plans to convert its 3-nm process R&D into a 1.4-nm process in June and thus reclaim sub-2-nm leadership from Samsung Foundry.