CMOS Depletion-mode technology holds many advantages
Article By : Wen Lin
The implementation of depletion-mode CMOS circuits could lead to many advantages in logic and memory.
Traditionally, the depletion MOSFET was classified as a linear device because the conduction channel between source and drain could not be pinched off and was thus unqualified for digital switching. The seed of this misconception was planted by Dr. Dawon Kahng, who invented the first depletion MOSFET – with only three terminals – in 1959. Lacking a reverse-biased PN junction in the substrate to pinch against, it was impossible to shut off the conduction channel of a three-terminal depletion MOSFET from the gate when the gate control voltage was varied between power and ground. Dr. Kahng’s depletion MOSFET could only be used as a variable resistor or non-inverting linear buffer. The depletion MOSFET has been used as a three-terminal linear device ever since.
When Frank Wanlass invented CMOS technology by using a complementary pair of four-terminal enhancement MOSFETs in 1963, Dr. Kahng had already moved on and ended his research work with depletion MOSFETs. When SPICE was developed ten years later, its success only reaffirmed the misconception that the depletion MOSFET was a three-terminal linear device, and not on par with the enhancement MOSFET.
The bias against depletion MOSFETs was finally discovered and rectified by this author in 2007 with the introduction of the four-terminal depletion MOSFET. With the additional substrate terminal to create a reverse-biased PN junction in the substrate to demarcate the conduction channel, the pinch-off of the conduction channel became possible, allowing depletion MOSFETs to be used as digital switches, and CMOS positive logic technology was finally born.
The discovery of positive logic operation from depletion MOSFETs was significant in three respects. Firstly, CMOS products can become intrinsically safe from damage caused by ESD events, even when they are handled without ESD protection. Secondly, the non-inverting buffer and 1T memory cell can save half of the cost for SRAM and DRAM. And lastly, since the gate control voltage always has the same potential as the conduction channel when the depletion MOSFET is conducting current, the gate leakage current of enhancement MOSFETs that stymied Moore’s Law between 2004 and 2009 suddenly disappears, regardless of how thin the insulator between gate and conduction channel has become. Moore’s Law is back again!
For an enhancement MOSFET, the potential at the gate is always opposite to the potential of the conduction channel when it is conducting currents; consequently, the insulator under the gate has to withstand a large potential difference. As the scaling progresses, leakage current through the ever thinner insulator can only get worse, becoming its Achilles’ heel.
The implementation of a depletion MOSFET is very much the same as an enhancement MOSFET, except the additional requirement to implant a shallow conduction channel below the insulator under the gate so that the conduction channel can be easily pinched off. A shallow conduction channel, however, limits the amount of current carriers to be implanted and retards the switching for depletion MOSFET. To overcome this difficulty, the conduction channel of depletion MOSFET is normally built in a tall and thin 3D structure so that it can be surrounded by the gate as much as possible, while offering as many current carriers as possible.
Additionally, the rule of source-pin assignment to build SPICE models for depletion MOSFETs should also be changed according to the occurrence of pinch-off. Traditionally, the source pin assignment of depletion MOSFET follows the same rule as enhancement MOSFET according to the induction of current carriers; consequently, SPICE can only simulate the depletion MOSFET as a linear device to be operated in the enhancement mode. Since it is pinch-off that produces the switching of state instead of induction of current carriers when a depletion MOSFET is operated in the depletion mode, SPICE must assign the source pin accordingly to simulate the depletion MOSFET as a digital switch.
Theory
The switching of state for MOSFET can be better understood through the transfer characteristics shown in Figure 1.
Figure 1 contains the transfer characteristics of all four MOSFETs: N type enhancement, N type depletion, P type enhancement, and P type depletion. The four transfer characteristics of MOSFETs shown in Figure 1 have been known since 1960. For instance, taking N type enhancement MOSFET as the example: the conduction channel is nonexistent and IDS = 0 when the gate control voltage VGS is 0 V. A conduction channel composed of electrons will be induced to allow current to flow through the drain and source terminals when the gate control voltage VGS is +V. In the enhancement mode of N type MOSFET, VGS must be positive to induce negatively charged electrons to switch the state so that the source terminal must be tied to the lowest voltage of the system for ground or substrate.
But for P type enhancement MOSFET, a conduction channel composed of positively charged holes will be induced to allow current to flow through the drain and source terminals when the gate control voltage VGS is -V. In other words, VGS must be negative in the enhancement mode of P type MOSFET to switch the state so that the source terminal must be tied to the highest voltage of the system for power supply.
The induction of current carriers is the rule that SPICE follows to assign the source pin to all MOSFETs before executing the simulation program.
It is also well-known that the behavior of N type depletion MOSFET is similar to N type enhancement MOSFET when VGS is positive in the enhancement mode; the only difference between the two is the amount of leakage current IDSS when VGS = 0V. An enhancement MOSFET should not leak any current when the gate is not energized so that IDSS must be 0 when VGS = 0V but a current of IDSS is allowed to flow through the conduction channel for depletion MOSFET when VGS = 0V.
In conclusion, the enhancement behavior of N type MOSFET occurs when VGS is positive while the enhancement behavior of P type MOSFET occurs when VGS is negative. But we never investigated the depletion behavior of N type MOSFET when VGS is negative or the depletion behavior of P type MOSFET when VGS is positive!
Of course, we never have the need to investigate the depletion behavior of N type enhancement MOSFET since it never leaks current when VGS is negative but we can’t ignore the depletion behavior of N type depletion MOSFET because the switching of depletion MOSFET yields positive logic operations which will be explained shortly. Likewise, we never have the need to investigate the depletion behavior of P type enhancement MOSFET since it never leaks current when VGS is positive but we can’t ignore the depletion behavior of P type depletion MOSFET.
Consider Figures 2 and 3, showing two switching circuits using P type MOSFET. For the enhancement MOSFET in Figure 2, when the input is 0V, VGS is equal to -V; a large current will flow through RL so that the output voltage will be close to +V. When the input is +V, VGS is equal to 0V; no current will flow through RL so that the output voltage will be 0V. The logic states of input and output are always opposite to each other.
But for the depletion MOSFET shown in Figure 3, when the input is 0V, VGS is equal to 0V; a large current of IDSS will flow through RL so that the output voltage will be close to 0V. When the input is +V, VGS is equal to +V, no current will flow through RL so that the output voltage will be +V. The logic states of input and output are always the same.
Likewise, consider Figures 4 and 5 below showing two switching circuits using N type MOSFET. For the enhancement MOSFET shown in Figure 5, when the input is +V, VGS is equal to +V; a large current will flow through RL so that the output voltage will be close to 0V. When the input is 0V, VGS is equal to 0V; no current will flow through RL so that the output voltage will be +V. The logic states of input and output are always opposite to each other.
But for the depletion MOSFET shown in Figure 4, when the input is +V, VGS is equal to 0V; a large current of IDSS will flow through RL so that the output voltage will be close to +V. When the input is 0V, VGS is equal to -V; no current will flow through RL so that the output voltage will be 0V. The logic states of input and output are always the same.
From the above four circuits, we can conclude that the enhancement MOSFET offers negative logic operations while the depletion MOSFET offer positive logic operations. P type depletion MOSFET is similar to N type enhancement MOSFET because both require a positive voltage to energize the gate; and the source terminal is connected to lowest ground voltage.
Likewise, N type depletion MOSFET is similar to P type enhancement MOSFET since both require a negative voltage to energize the gate; and the source terminal is connected to highest power supply voltage.
The control gate of an enhancement MOSFET is energized when current carriers are induced in the conduction channel; in contrast, the control gate of a depletion MOSFET is energized when the conduction channel is pinched off.
The operation of depletion MOSFET can also be explained by Figure 6, which shows the pinch-off of P type depletion MOSFET when the gate is energized and connected to +V. The positive voltage at the gate will induce negatively charged electrons to accumulate below the insulator and to nullify the holes in the conduction channel to create a zone without current carriers. At the beginning, this zone will appear near the source terminal – which is tied to ground potential – and the zone will keep expanding until the P channel is completely pinched off. The pinch-off will always occur near the source terminal first since it is tied to 0V ground which has the lowest potential of the system while the voltage at the output drain terminal can never be lower than 0V.
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—Wen T. Lin is a veteran hardware design engineer with broad experience including analog, RF, and high-speed digital.