Coherent backplane IP halves memory latency
Article By : ARM
CoreLink CMN-600 and CoreLink DMC-620 are complete coherent backplane IP solution for the ARMv8-A architecture.
ARM has rolled out the third generation of its coherent backplane technology, which it says has been optimised to deliver the scalability, performance and efficiency demanded across multiple markets including 5G networks, data centre infrastructure, HPC, automotive and industrial systems.
The CoreLink CMN-600 coherent mesh network interconnect and CoreLink DMC-620 dynamic memory controller enable the latest ARM-based SoCs to improve data throughput by a factor of five and halve memory latency.
Optimised with the latest ARM Cortex-A processors, CoreLink CMN-600 and CoreLink DMC-620 are complete coherent backplane IP solution for the ARMv8-A architecture. Designers and system architects can scale high-performance SoC designs from 1 to 128 Cortex-A CPUs (32 clusters) with native ARM AMBA 5 CHI interfaces, the industry standard specification for high-performance on-chip communication.
Other key benefits and features include:
- New architecture achieving higher frequencies (2.5GHz and higher), 50% lower latency
- 5x higher throughput and more than 1TB/s of sustained bandwidth
- New Agile System Cache with intelligent cache allocation to enhance any sharing of data between processors, accelerators and interfaces
- Supporting CCIX the open industry standard for coherent multi-chip processor and accelerator connectivity
- CoreLink DMC-620 includes integrated ARM TrustZone security and supports 1 to 8 channels of DDR4-3200 memory and 3D stacked DRAM for up to 1TB per channel.
