Common silicon issues in analog IP integration

Article By : Kedar Patankar

Even novel process enhancements are coming up short in the face of massive gate counts placed side by side with analog circuitry in SoC designs of 16nm and below.

Despite the fears of the last decade that Moore’s Law had finally reached its end, the microelectronics sector has continued to adapt to new physical constraints and product requirements through sustained innovation and creativity. A major portion of that creative energy has gone into the development of analog, RF and mixed-signal blocks as embeddable IP.

Figure 1 The block diagram highlights a multimedia SoC design. Source: P2F Semi

The selection of analog/RF/mixed-signal IP now available is both broad and deep. One can find a multitude of hardware blocks in 7 nm (and in some cases even 5 nm) in the following major categories:

  1. PLL and DLL: offered in a wide range of speed, jitter and power specifications
  2. DAC and ADC: available with resolutions of 8-bit to 24-bit and up to 300 MSPS
  3. PHYs and SerDes: targeted at a broad selection of markets such as wireless (Wi-Fi and 5G), networking (LAN, WAN and Storage), computing (USB, PCIe, MIPI) and memories (DDR, including G and LP variants, as well as HBM and many others)
  4. Smaller components that can be assembled to create personalized analog front-ends (AFEs), power management functions, and RF modules

The industry has produced a steady stream of process technology advancements to support the never-ending demand for higher gate counts, lower power, greater performance and increased functionality. That includes triple well isolation, silicon-on-insulator, P+ guard rings, FinFET and trench isolation. Many of these features contributed to the proliferation of analog, RF, and mixed-signal IP we see today. These substrate additions also reduced the magnitude of some of the complications with which designers have been contending in ultra-deep submicron—problems such as analog noise sources hidden in slew rates, impedance matching and termination complications, and circuits that support tremendous bandwidths.

Yet even novel process enhancements are coming up short in the face of massive gate counts placed side by side with analog circuitry in SoC designs of 16 nm and below. In fact, the signal and power integrity challenges presented by large, high-performance digital blocks in close proximity to analog/RF macros are spreading from chips into packaging and PCBs, both of which are struggling to keep pace with silicon advances. The SoC designers increasingly find themselves compelled to expand their range of effort into these other two realms to ensure their chip designs will function as intended.

This multi-part article series explores how embedded analog and RF IP cores can negatively influence chip, package and PCB function—the effects of which are many and varied. We’ll also discuss what can be done to safeguard against these problems at all three levels and how these solutions can be mutually reinforcing.

Silicon practices

Over the last two decades, attempts to create a unified tools and methodology flow for both analog and digital circuit design have so far proven to have been in vain. There is, however, general agreement on the basic outline of the analog flow, as presented in Figure 2.

Figure 2 The view showing the basic analog design flow. Source: P2F Semi

Though the flow may seem rather straightforward, the devil is in the details.

Analog circuitry is decidedly sensitive to how circuits are placed and routed. Design rules—trace and via pitch, differential signaling, and extra ground pins—help avoid or at least reduce substrate coupling and proximity effects that result in EMI problems. That’s why design rule checking (DRC) is part of the physical verification effort after layout. Layout versus schematic (LVS) checking is also part of the same step to verify intended connectivity.

Parasitic extraction directly affects identification of potential coupling sources with back annotation of parasitics often resulting in schematic and layout changes. Unfortunately, this will affect timing, dynamic range, load, gain, and power and generate a fresh new set of parasitics. Iterative loops which return to the beginning of the design flow are thus a tragic necessity, which is why analog design is considered to be much more of an art than a science.

Integration of analog blocks

So, integrating of the resultant analog block(s) into the overall ASIC/SoC design presents a whole new set of concerns. For both digital and analog circuit blocks, chip floor planning will be constrained by the optimal location of each block, pin placement, I/O locations, critical paths, power and signal distribution, and the size of the chip and its aspect ratio. Analog IP is particularly sensitive to most of these issues, and the fact that analog blocks are also hardmacs complicates all of the above.

Once a chip’s blocks are placed, best routing practices include implementing all critical paths first, whether analog or digital. However, when it comes to non-critical paths, analog signals should take precedence. Furthermore, whether or not a given analog signal is critical, all analog routing requires special consideration in terms of matching parasitics, minimizing coupling effects, and avoiding excessive IR drops. It’s accomplished through employing the various shielding techniques for analog signal routing, keeping traces short, routing return signal paths by the most direct route, differential signaling, and so forth.

Beyond these broad approaches for integrating analog content on-chip, different categories of analog circuitry may also need particular attention. DACs and ADCs are a perfect example.

There are design considerations when using a DAC or ADC beyond its resolution and sampling rate—namely, its spec’d signal to noise ratio (SNR), the effective number of bits (ENOB) rating, and power consumption. Following Nyquist’s sampling theorem—which states that an adequate digital recreation of an analog signal requires sampling at more than 2x the analog Fmax—can by itself cause bandwidth, power, and bit synchronization challenges for very high-performance applications.

Wireless is particularly problematic from a sampling point of view, while audio is generally the most demanding in terms of resolution. That’s where a parameter such as ENOB has particular relevance. No matter what the advertised resolution may be for a given DAC or ADC, pushing such a block past its ENOB will degrade its SNR performance with potentially significant consequences to the genuine usefulness of the block.

Above and beyond all this is the fact that analog block design and integration into the context of an SoC or ASIC is simply not as ‘clean’ and predictable an engineering effort as the digital section of the chip. Experience, flexibility, and adaptability are the determining factors for success.

Traditionally, chip design teams considered their concern in properly integrating both digital and analog/RF/ mixed-signal blocks into an SoC design to reach no farther than this. But as we will illustrate in the upcoming articles of this series, it’s no longer the case. The dimensions of SoC design work are ineradicably expanding, and teams will need to grow their skillsets and practices considerably in order to survive this transformative period.

This article was originally published on Planet Analog.

Kedar Patankar, chief technology officer (CTO) at P2F Semi, is a semiconductor industry veteran with 23 years of experience in design, development, and customer relations.


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