CPLD’s internal oscillator does autocalibration

Article By : Rafael Camarota

Read about an autocalibration sequence that synchronises a CPLD's internal oscillator with an external crystal oscillator, enabling ±0.3% accuracy.

The MAX II CPLD family from Altera features an internal oscillator that dissipates much lower power than do external oscillators. The internal oscillator has an accuracy of only ±25%, sometimes limiting its usage. For example, many applications, such as an interval timer for data gathering and a real-time clock, require more accuracy—±0.1 and ±0.001%, respectively. A simple circuit uses an external crystal oscillator to calibrate a timer to better than ±0.3% accuracy. The internal oscillator sustains the calibrated output even after you shut down the external oscillator to save power. The circuit maintains this accuracy as long as the VCC and temperature are stable. Whenever you enable the external oscillator, the circuit quickly recalibrates if necessary.

A remote industrial sensor should sample an event every second. To save power, a timer powers down most of the sensor circuit most of the time to increase battery life. The system powers up for a short sample; then, the system, except for the CPLD, powers down, which times the period to the next power-up, sample, and calibration. Most of the components of a wireless receiver in a power-saving mode power down; however, the CPLD timer and wake-up mode stay on for monitoring and calibration.

[internal CPLD counter]
__Figure 1: __*This internal CPLD counter first synchronises with an external clock to 60.3% accuracy and stays at that frequency until reset.*

Figure 1 shows a simple circuit with a crystal oscillator with typical ±100-ppm accuracy; an EPM240 CPLD with a ±25%-accurate, 4.4MHz internal oscillator; and an autocalibration circuit in the programmable-logic array that generates a ±0.3%-accurate, 10kHz clock. For simplicity, the figure omits the external oscillator's VCC1 power-down or enable circuit and the application logic using the 10kHz clock. The 33.33MHz clock drives a reference counter, which is a divide-by-3333 LPM (library-of-parameterized-macros) counter. You derive LPM blocks from Altera's Quartus II LPM. The COR (carry-out-reference) signal feeds back to the count-enable input such that the COR signal stays at one after reaching the 3333 count until you apply the reset signal. The divide-by-3333 counter generates a 0.1-msec reference period. The 4.4MHz LPM oscillator drives all other clocks in the autocalibration circuit: the source counter, a 10bit counter with a power-up asynchronous reset; a synchronous reset; and a 10bit output source. The 4.4MHz clock also drives the 10bit up/down-adjust counter that presets to 333 at power-up. It has an enable input, an up/down-control-input signal, and a 10bit output adjustment. The adjust and source drive the inputs of the compare LPM that generates a one on the COC (carry-out-from-comparator) signal when adjust equals the source. The COC signal drives the synchronous input of the source counter, making it a free-running counter with a period equal to the adjustment signal. An LPM register converts the COC signal into a synchronous, 10kHz pulse when you calibrate the system. The control-logic block generates enable, up/down, and synchronous-reset output signals based on the COC and COR inputs.

[state machine]
__Figure 2:__ *This state machine shows the transitions of the control block in Figure 1. *

Leave a comment