Create high-performance SoCs using network-on-chip IP

Article By : Andy Nightingale

Don't spend years developing a NoC in-house. Increase productivity, reduce risk and speed time to market using network-on-chip interconnect.

A system-on-chip (SoC) containing a million transistors was considered a large device in the not-so-distant past. Today, SoCs commonly contain up to a billion transistors. Consider, for example, the recent case study with and its new machine learning (ML) chip called MLSoC; it provides effortless machine learning at the embedded edge.

This MLSoC, created at the 16-nm technology node, comprises billions of transistors. As is almost invariably the case in today’s SoC designs, the MLSoC is composed of a sophisticated mix of off-the-shelf third-party intellectual property (IP) blocks coupled with an internally developed machine learning accelerator (MLA) IP.

Figure 1 The MLSoC chip combines host processor and ML accelerator capabilities in one device. Source:

Third-party IPs are well-known and standard functions, such as processor and communication cores—Ethernet, USB, I2C, and SPI—and peripherals, the sort of processes not worth the time and effort to develop internally. The “secret sauce” that differentiates this SoC from its competitors is the MLA, which provides 50 trillion operations per second (TOPS) while consuming a minuscule 5 watts of power.

One problem with combining hundreds of IPs from various vendors is that multiple interconnect protocols have been defined and adopted by the SoC industry—OCP, APB, AHB, AXI, STBus, and DTL—and each IP may use a distinct protocol. Also, each IP may support a different data width and run at a separate clock frequency. As you can imagine, getting these IPs to talk to each other can be daunting.

Enter the NoC

The best solution for connecting hundreds of disparate IPs is to employ a network-on-chip (NoC). Using buffers and switches, the NoC passes data packets between initiator and target IP blocks. Each packet contains a header, which includes an ID with the source and destination addresses, and a body that encompasses the data. Large numbers of packets can be in flight at the same time.

Each IP will have one or more interfaces called sockets. Network interface units (NIUs) connect the IP sockets to the NoC and serialize and packetize the data while accommodating each IP’s data width and clock frequency requirements.

Developers typically envisage IPs as having square or rectangular footprints on the surface of the silicon chip. Many developers fail to recognize that the NoC is an IP, albeit one that spans the entire chip.

Homegrown or off-the-shelf?

SoC developers must decide whether it’s better to implement the NoC in-house or acquire it from a third-party purveyor. For many teams, this is a non-issue because they lack the time, resources and skills required to develop a full-function NoC from the ground up.

Creating a NoC suitable for a modern SoC can easily require six engineers working for two years. And then there’s the problem of debugging the NoC and the rest of the design simultaneously. The only realistic solution that reduces risk, speeds time to market, and equates to time to monetization is to employ a proven off-the-shelf NoC from a trusted vendor.

Technical benefits

Implementing a NoC requires more than attaching NIUs to IP sockets and determining the locations of any switches and the size and locations of any buffers. Since the NoC spans the entire chip, it will be necessary to introduce pipeline stages (registers) for the physical layout team and tools to meet the SoC’s performance and timing specifications.

Designs involve iterations. Performing iterations in the front-end design portion of the process is much faster than involving both the front-end and back-end physical layouts. If the front-end design engineers insert these pipeline stages by hand and fail to use enough in the right places, the back-end physical implementation team will fail to meet its goals, causing the project to be returned and reworked by the designers.

Unfortunately, architects typically address this issue by over-engineering the problem and inserting too many pipeline stages. Although this will help the physical design team to meet timing, any pipeline stages that are surplus to requirements consume die area, burn power, and increase latency.

One way to address this is by using physically aware NoCs. This means that as soon as the physical layout team provides the proposed locations of the various IP blocks, this data can be used to automatically determine the optimum number and placement of any pipeline stages. By speeding up the physical layout process, the number of time-consuming back-end to front-end iterations required to achieve timing closure is significantly reduced.

One such NoC is FlexNoc 5, which is physically aware and has additional options. For extreme designs with hundreds of IPs and 1024+ bit-wide connections, the FlexNoc XL option provides a large-capacity mesh-NoC generator capability. The FlexNoC 5 Advanced Memory option is available for architectures involving complex memory interleaving schemes and non-contiguous address bits. This option uses multi-channel reorder buffers that avoid ordering rule blocks and response serialization bottlenecks yet allow concurrent memory channel reads.

Figure 2 The physically aware network-on-chip IP offers productivity enhancements. Source: Arteris

Some designs are considered safety-critical, which means a failure or malfunction may result in death or serious injury to people, loss or severe damage to equipment or property, and environmental harm. In the case of this type of design, FlexNoc 5 fabric IP can be complemented by the FlexNoC Resilience option. This package can help designers to implement the functional safety features required for compliance with the automotive ISO 26262 and IEC 61508 standards. It also provides hardware reliability for enhanced enterprise SSD endurance.

Why off-the-shelf NoC IP

The only way to manage complex SoC designs is to use NoCs. Rather than spending years and burning engineering resources developing a NoC in-house, it’s better to save time, reduce risk and speed time to market by using a trusted and reliable off-the-shelf NoC.


This article was originally published on EDN.

Andy Nightingale, VP of product marketing at Arteris, has over 35 years of experience in the high-tech industry, including 23 years spent on various engineering and product management positions at Arm.


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