DC/DC converters have considerably higher EMI than the LDO regulators, so it’s important to design with EMI in mind.
Every year, automobile manufacturers equip cars with growing numbers of sensors and features, increasing the electronics content in the car and driving up its power needs. As power levels increase, engineers who may have relied on low-dropout linear regulators (LDOs) may now need to use a buck topology to meet target efficiencies.
A buck can deliver more power than a typical LDO at higher efficiencies but has a drawback—its switching nature creates electromagnetic interference (EMI), which can be a serious issue for automotive applications. Luckily, there are many tricks and tools engineers can use to reduce EMI, including optimizing the board layout, leveraging IC features, and adding circuitry.
DC/DC converters generate EMI from input ripple, electric and magnetic coupling to nearby circuits, and electromagnetic radiation. EMI can interfere with the AM/FM radio receiver and other sensitive equipment like the head unit or advanced driver assistance system (ADAS) sensors. Significant EMI can create static noise or other types of noise in the radio and head unit audio, interfere with ADAS sensors, and degrade performance of other systems.
To prevent such significant degradation, engineers need to design systems that meet official standards such as Comité International Spécial des Perturbations Radioélectriques (CISPR) 25 Class 5. Because a poor layout can cause any device to fail EMI limits set by standards bodies, it’s important to follow good layout optimization practices during the board layout. The most important practices for a buck converter are to:
These two basic rules will dictate where engineers place certain components in order to minimize EMI.
Unfortunately, even the most optimized PCB layout cannot prevent all EMI-related issues. In addition, it’s often not possible to optimize the layout for EMI as much as we’d like due to board size and shape or time constraints. A very compact layout, for example, may require you to place the power inductor on the bottom side of the board, or to place input capacitors slightly farther from the IC than is optimal to minimize EMI.
These and other layout constraints can cause EMI that degrades system performance. Even with experience and care, a board may require further optimization. These additional board revisions take up time and money. So what else can you do in addition to an optimized layout to minimize EMI for your application?
Going around board layout limitations
If it’s not possible to optimize the layout for optimal EMI, some DC/DC converters offer a number of package and feature improvements at the device level to help minimize EMI and make it easier to meet the CISPR 25 Class 5 limits. These features make the board design more layout-agnostic; in other words, they can help make up for layout shortcomings.
For example, spread spectrum is a feature that spreads harmonic energy to reduce the maximum values of peak and average EMI measurements. It does this by dithering the switching frequency—plus and minus some percentage—to spread the spectral density. Spreading ±2%, for example, would see a complete blend or overlap of harmonic energy on the 25th and higher harmonics instead of a fixed frequency, which would maintain harmonic spikes spaced at the fundamental frequency. The energy is spread evenly in the higher frequencies, resulting in a lower envelope of measured values, requiring less filtering and less layout optimization, and thus saving time and money.
Slew-rate control is another feature that helps improve EMI performance. A major source of EMI is the switch ring. The switch ring is caused by the fast turn-on of the high-side FET, which quickly pulls current from the input capacitors, resulting in a ring in the hundreds of megahertz caused by the resonance of the input parasitic loop inductance and the parasitic capacitance of the low-side FET. Slowing this rise time slows this immediate current draw, which results in less ringing and less EMI. It is possible to slow the rise time by adding a resistor in series with the boot capacitor (on the order of a few ohms) and some devices have a dedicated boot resistor pin. There is a trade-off here: slowing the slew of the FETs minimizes EMI, but also increases switching loss, which decreases efficiency.
There are also package-level features that help suppress EMI. One example is TI’s HotRod package, which eliminates internal bond wires, as shown in Figure 1. Discontinuous current causes ringing on the switch node in the hundreds of megahertz, which couples and radiates, causing EMI. Removing bond wires in the path of the high di/dt loop of the input capacitors’ discontinuous current reduces the loop inductance. That, in turn, reduces the energy in the ringing, which reduces EMI. Devices such as the LM61460-Q1 and LM53635-Q1 are available in the HotRod package.
Figure 1 This cross-sectional view allows engineers to compare standard wire-bond quad flat no-lead (QFN) packaging and TI’s HotRod QFN. Source: Texas Instruments
Other package-level features include optimized pinout. Devices can improve EMI performance by organizing the pin placement so that critical paths such as input capacitor can remain as small as possible. Devices often place the VIN and GND (or PGND) pins adjacent to one another to give an optimized place for a capacitor to connect.
Taking this a step further is symmetrical pinout. Placing VIN/PGND symmetrically on either side of the package allows the input loop magnetic fields to self-contain, which further reduces EMI. Many DC/DC buck converters such as the LMR33630, LMR36015, LM61460, and LMQ61460-Q1 have symmetrical VIN/PGND pin pairs (Figure 2b).
Integrated input capacitors
The next generation in EMI optimized packages uses integrated capacitors to further reduce the input parasitic inductance. LMQ61460-Q1 includes two integrated input bypass capacitors on either side, one for each VIN/PGND pair. These capacitors are the dark rectangles straddling the upper- and lower-right pin pairs (VIN and PGND) shown in Figure 2a. Figure 2b shows the device pinout for reference.
Minimizing high-frequency EMI is of particular importance, because higher input voltages and higher output currents common in automotive applications can worsen problems in this area.
While it’s true that EMI presents challenges in automotive applications, design engineers aren’t out of options if they are experiencing board layout constraints. There are many ways to address this challenge, from strategic device pinout to integrated features such as low-inductance packaging, slew-rate control, spread spectrum, and integrated capacitors.
Such features enable engineers to relax the requirements of strict EMI layout optimization in exchange for a well-rounded layout, allowing more room for optimization for better thermal performance and/or a smaller solution size. These features improve your designs to confidently meet EMI limits set by standards bodies.
This article was originally published on EDN.
Zachary Imm is automotive product marketing manager at Texas Instruments.