Debugging approach for resolving noise issues in a PDN

Article By : Nitin Saxena , Arpit Jain , Amit Kumar & Siyaram Sahu

Target impedance is the most important factor of a PDN. Keep it in its range and avoid noise issues in the power network.

In board designs, power integrity and signal integrity are very important factors and power delivery network (PDN) design plays a vital role in analyzing these factors. In the beginning of board designs, PDN performances were not considered as major criteria. In today’s scenario with development in semiconductor technologies, for devices with lower voltage, higher current, and low voltage noise margin, PDN performances should be optimized to meet the device specifications.

This article explains the PDN, target impedance range, and discusses the components required to keep the target impedance in its range. It also discusses the challenges and effects of the PDN components including the voltage regulator module, bulk decoupling capacitors, and power plane parasitics. A case study also presents a debugging approach for resolving noise issues in the PDN in the absence of bulk and decoupling capacitors.

PDN design is getting more complex and difficult with advancements in semiconductor technologies. There are several types of semiconductor products for which power distribution is very necessary to run them properly. Nowadays, electronic boards are getting densely packed and the number of on board voltages are increasing rapidly. So, it is essential to board designers to deliver the right power to all the on-board devices with optimum space and highest efficiency. Also, as clock frequency rises, and more and more functions get integrated into a single SoC, power consumption increases. Along with that, strict noise requirements are also increased for proper functioning of the device, which creates various challenges towards the design of a PDN, i.e. power quality also limits the performance of circuits and has become a determining factor in how reliably they work.

Here, the reactive part of the system is comprised of chip capacitance, package inductance, and structures of the PCB. This reactive part of the system, often referred to as system reactance, usually gets ignored by designers, and always dominates IR drop. Resonant structures get formed due to system reactance which stores and releases energy in different frequency bands. The whole of the system should be contemplated in order to estimate the impedance peaks in the frequency domain and overshoots and undershoots in the time domain. The system should be analyzed as a whole because estimation of resonances is not possible by only analyzing the board, chip, and package individually. [4]

Methods to distribute voltage and power to all the active devices requiring power and to keep the noise below an acceptable level, are discussed below, followed by a case study that discusses the scenarios which can arise in the absence of bulk and decoupling capacitors and how to debug those scenarios.

Power delivery network
The ultimate purpose of a PDN is to supply noiseless power to the devices on the PCB. It consists of all the interconnects in the path from the voltage source to the circuits on the PCB. Figure 1 shows a very simple depiction of a PDN.

ZPDN is an impedance of the path between VRM and the load. The measure of voltage ripple, which can be seen on a given power rail, is comparable to the transient current (ITRANSIENT) incorporated with that rail and the impedance (ZPDN). [3]

Based on Ohms law:

So VRIPPLE is proportional to transient current and impedance. But transient current is totally specific to the application and can only be determined during the run time. Board designers have no control of this parameter. So, the only way left for designers to minimize voltage ripple is reducing ZPDN, as this is under the control of designer. To design a system which is having noise voltage ripple within the desired limit, the PCB must be designed in such a way that ZPDN meets a certain impedance, that is called ZTARGET.

Figure 1 System PDN [3]

Target impedance (ZTARGET)
The first step towards any PDN design is to identify the target impedance for a wide frequency range. This is essential as the current transients can exist at different frequencies, which makes it a necessary requirement that target impedance be established for all frequencies and not just at DC.  The target impedance is defined as:

Max Transient Current = maximum change in current over a defined frequency range; %Ripple = maximum expected ripple (noise) on a voltage rail.

In order to classify design guidelines for any PDN, a target impedance is identified that is low enough to deliver power with optimum quality and at minimum cost i.e. an efficient PDN design minimizes the impedance such that ZPDN either meets or is lower than ZTARGET. It is called target impedance because if the actual impedance is greater than target impedance then then probability of circuit malfunction will be very high, whereas if the actual impedance is less than target impedance, it unnecessarily increases the cost. From a design standpoint, certain trade-offs must be made to achieve balance between cost and performance of the circuits depending on the target impedance. Apart from that, it may or may not be possible under all scenarios to design a PDN with ZPDN under ZTARGET. [3][4]

PDN and its components
A PDN requires various components to establish ZTARGET over a wide frequency range. It can either be very simple or extremely complex depending on its design. A simple PDN design can be classified as one which receives its power through some edge connector which is connected to an external power source, i.e. from a source which is not present on the board. From the edge connector the power can be distributed to the devices through appropriately routed traces. Similarly, a complex PDN design can be classified as one which has one or more voltage regulator modules (VRM’s), some components or circuits to improve power quality such as a decoupling capacitor, bulk capacitor or multistage LC filters, and a closely spaced system of ground and power planes to distribute power along the board such that the planar capacitance is uniformly distributed [2]. A complex PDN design can be seen in Figure 2.

Figure 2 A PDN consisting of VRM, bulk and decoupling capacitor, and power and ground planes [1]

PDN components

As discussed, the components of PDN and their effects can be categorized as follows.

Voltage regulator modules (VRM)

VRM are usually designed to regulate the output voltage at a constant level for all possible load conditions. It takes one voltage as the input and converts it to another voltage at the output; i.e. for a 5V input, the output can be 3.3V, 1.8V, or any other voltage depending on the design. At low frequencies, between 1kHz to several hundred kHz, the VRM has low impedance and can respond to the rapidly changing load conditions. At frequencies higher than few kHz, the VRM changes into high impedance and is incapable of supporting the transient current requirement. [1]

Decoupling capacitors

Since the VRM helps maintain the ZPDN up to only a few kHz, decoupling capacitors are required to maintain the ZPDN at higher frequencies. A decoupling capacitor can be modelled as a series combination of R, L, and C where:

R = equivalent series resistance (ESR) of the capacitor, L = equivalent series inductance (ESL) of the capacitor, and C = the capacitance of the capacitor.

The equivalent circuit thus formed is called an RLC series resonant circuit. The L and C components define the resonance frequency of the circuit, also called the self-resonant frequency (SRF) and is represented by: 

The resistive component (ESR) of the capacitor is a function of frequency, i.e. it changes with changes in frequency. At SRF, the RLC circuit is purely resistive and the total impedance is equal to the ESR. This ESR should be lower than the ZTARGET for an efficient PDN design. Above SRF, the capacitor’s impedance increases with increases in frequency due to the inductive component (L). [3]

A large number of capacitors are connected in parallel to establish low ZPDN. For a PDN, which has many identical capacitors connected in parallel, every time the number of capacitors get doubled, the impedance will get divided by 2. Figure 3 represents this effect of connecting a few identical capacitors in parallel. [1]

Figure 3
Impedance vs frequency plot for identical capacitors in parallel

Traditionally, a combination of capacitors with different values are chosen instead of several identical capacitors to achieve the ZTARGET. Using many identical capacitors does reduce the ESR significantly near the resonant frequency but choosing capacitors with different values improves the frequency performance with a slight increase in ESR. However, this combination of different value capacitors produces an unwanted phenomenon called ‘‘anti-resonance’’ as shown in Figure 4. The anti-resonant peak is developed when one of the capacitors in the circuit is still capacitive while the other capacitors have gone inductive. These peaks are formed when multiple value capacitors having low ESR are placed on pads with high inductance. Minimizing the inductance is the best possible way to lower the anti-resonant peaks. [1][3]

Parasitic inductance

As discussed in the previous section, reducing the inductance helps improve the frequency performance of the decoupling capacitors by a great extent. Figure 5 shows the formation of current loops when the current passes through the decoupling capacitor, travelling along the power plane, vias, pads, and the ground plane. The inductance seen by a capacitor is defined by this current loop and the most effective way to reduce this inductance is by minimizing the loop area. [1]

The overall inductance seen by the capacitor, due to the current loop, can be further classified as mounting inductance, spreading inductance and via inductance as shown in Figure 6. Mounting inductance is mainly associated with the placement of the capacitor on the board.

Figure 4
Anti-resonance of parallel capacitors [2]

Figure 5
Current loop formation due to pad, vias, and power planes [1]

The spreading inductance is mainly dependent on how the board is designed. It is defined as a function of the thickness (h) of the dielectric between the reference plane (power & ground) and distance (d) of the capacitor w.r.t. the device. Placement sensitivity of the capacitor can be reduced by decreasing the dielectric thickness (h) which allows us to place the capacitors away from the device. [3]

The capacitor effectiveness also depends on the via inductance as the current travels though the via field before it reaches the device. A small trace, existing between the vias and pads, can also increase the inductance enormously. The cumulative inductance observed by any capacitor is a sum of the mounting inductance, the spreading inductance, and via inductance.

Thus, to reduce the inductance seen by a capacitor, the following design rules can be identified:

  1. Vias must be placed close to the capacitor.
  2. Via pitch must be minimized for the vias between the power/ground plane.
  3. Opposite polarity vias must be placed close together and vice versa.
  4. The vias must be connected to the capacitor pads through short, wide traces.
  5. Capacitors should always be placed near their corresponding power and ground planes.[3]

Figure 6
Capacitor mounting, spreading inductance, via inductance on PCB [3]

PDN-related issues

In this section we discuss the challenges faced during current measurement through external loops.

During SoC validation, it is required to remove all the bulk and decoupling capacitors from the voltage rail to achieve the required slew rates (~100kV/s) during current profiling. As seen in Figure 7, an external loop is required in the path to capture the current on the voltage rail with the help of the current probe.

As can be seen, we have disturbed a PDN by removing all the decoupling and bulk capacitors and added the introduction of an external loop for current measurement; this has disturbed the target impedance (ZTARGET) of the voltage rail for which it was designed.

Because of these reasons, we were getting sinusoidal noise on the current and voltage as seen in Figure 8 and we were not able to profile the current properly. As we dug deeper into this issue, it was found that when the external loop was removed, the voltage noise was gone and the same should be done for the current noise as well. But we were not able to measure current noise, as no external loop was present to capture current. But it was confirmed that noise is mainly due to the external current loop which was being used to measure current.

After debugging, a couple of solutions were found for this issue. Both solutions are inclined towards increasing the inductance of the external loop, with which we could affect the target impedance of the PDN and hence be able to solve the issue.

Figure 7
External loop for current probing

Figure 8
Sinusoidal noise on current and voltage

Use long thin wire for external loop

As we have explained before, by introducing an external loop, we have disturbed the characteristics of the PDN. And because of this we were getting sinusoidal noise on the current and voltage rails. We further debugged this and found out that by changing the length of the external loop, the noise amplitude was changing. And with one long thin wire, as seen in Figure 9, we found that no noise is observed at the output.

So, we checked with different long wires and found that while using long thin wires, noise is not appearing at the current and voltage output. We can see in Figure 10 that there is no noise present at the output and we can measure the current profile without any issues. We can see in this figure that the current noise is following the voltage noise. If no noise is present at the voltage, then the same applies with the current also.

Figure 9
Long thin wire external loop

Figure 10
Current and voltage profile with long thin wire

Wind the wire around the current probe 

We observed that, the noise is sensitive to the current loop used to probe the current. So, we explored the current probe literature and found some interesting ways to use the current probe. Transformer concepts are applied here to increase probe sensitivity by looping the conductor through the probe multiple times (Figure 11).

Sensitivity of the probe is directly proportional to the number of loops around the probe. By doing this, we have also solved the problem of noise at the current and voltage rail.

Reason behind the solutions

We found two solutions for the current noise issue, but in the end, we found that the reason was the same for both solutions: target impedance. With both solutions, we are trying to increase effective inductance of the path by introducing long thin wires or with multiple loops around the current probe. So, by increasing the effective inductance of the path, we are somehow compensating the disturbance at the PDN which occurred due to removing the decoupling caps and adding extra loop between the path.

Figure 11
Looping the wire around the current probe increases probe sensitivity.

So, the whole debug approach is to match the target impedance of the path so that the PDN will not get disturbed. Target impedance (ZTARGET) is the most important factor of a PDN. If we are playing with ZTARGET by introducing or removing anything (R, L, C) from the path, we need to compensate the same so that ZTARGET will remain constant; this will avoid noise issues in the power network.


[1] “Power distribution system design methodology and capacitor selection for modern CMOS technology,” L. D. Smith, R. E. Anderson, D. W. Forehand, T. J. Pelc, and T. Roy, IEEE Transactions on Advanced Packaging, vol. 22, no. 3, pp. 284–291, 1999)

[2] “Power Distribution System, Calculating PDS Impedance,” Douglas Brooks, Ultracad Design, Inc

[3] “AN 574: Printed Circuit Board (PCB) Power Delivery Network (PDN) Design Methodology,” Altera Application Note, May 2009

[4] “System Power Distribution Network Theory and Performance with Various Noise Current Stimuli Including Impacts on Chip Level Timing,” Larry Smith, Shishuang Sun, Peter Boyle, Bozidar Krsnik, IEEE 2009 Custom Integrated Circuits Conference (CICC)

[5] “Packaging and Power Distribution Design Considerations for a Sun Microsystems Desktop Workstation,” L.D.Smith, Electrical Performance of Electrical Packages Conference, Oct, 1997.

[6] “Modeling, Simulation and Measurement of Mid-Frequency Simultaneous Switch Noise in Computer Systems,” Wiren D. Becker et al., IEEE Transactions on Components, Packaging and Manufacturing Technology – Part B, Vol. 21, No. 2, May 1998.

[7] “Decoupling Capacitor Calculations for CMOS Circuits,” L.D.Smith, Electrical Performance of Electrical Packages Conference, Nov, 1994.

[8] “Modeling and Simulation of Thin Film Decoupling Capacitors,” K.Y. Chen, W.D. Brown, and L.W. Schaper, Electrical Performance of Electrical Packages Conference, Oct 1998.

[9] “ESR and ESL of Ceramic Capacitor Applied to Decoupling Applications,” Tanmoy Roy, Larry Smith, John Prymak, Electrical Performance of Electrical Packages Conference, Oct 1998.

[10] “Effectiveness of Multiple Decoupling Capacitors,” C. Paul, IEEE Transactions on Electromagnetic Compatibility, vol. 34, no. 2, May 1992

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