RT PolarFire offers huge potential to advance re-configurable on-board digital processing for the space industry.
In my opinion, a flash FPGA is the ideal, re-configurable, digital on-board processing technology for space applications; it’s non-volatile yet can be re-programmed during prototyping and in-orbit. Your intended functionality, i.e. the configuration, is stored as a charge within a floating-gate transistor, which is immune to radiation upsets.
The non-volatility of flash-based FPGAs avoids the need for an external memory to re-boot your intended functionality at power-up. This saves physical space on your PCB, reduces power consumption, and in some cases, eliminates the need for an extra voltage regulator. Overall, the use of a flash-based FPGA rationalises your BOM!
The fabric of flash-based FPGAs differs from hardened SRAM devices and, fundamentally for space-grade parts, requires significantly fewer transistors to store each bit of configuration data, e.g. 12 vs. 2. Hence for the same geometry, flash-based FPGAs consume less power. The resulting finer granularity within a flash fabric allows for very high logic utilisation, enhancing routing efficiency and performance.
Previously I discussed the release of Microchip’s 352-pin, CQFP version of its 65-nm RTG4 FPGA. I was intrigued by this part as it offers the space industry the performance and power-consumption advantages of 65-nm ultra deep-submicron technology if you do not actually need 720 I/O. The CQ352 contains the same die as the original RTG4150-G1657, but has been placed in a more ‘user-friendly’ package which satellite manufacturers traditionally find easier to assemble and mount. 166 I/O and 4 high-speed serial links are available. Simulations predicted the total device power consumption and the percentage contribution due to the I/O.
Figure 1 Here you’ll see the 1657-column RTG4 FPGA and its 352-pin CQFP variant.
I want to continue the discussion by introducing Microchip’s 28-nm RT PolarFire device. This uses SONOS technology, which is similar to flash in that it is non-volatile and re-configurable, however, it allows the use of lower voltages to program and erase the floating gates to fit with a 28-nm process. With almost 500,000 logic elements, 33 Mbits of embedded SRAM, 1,500 DSP blocks, >1 Gbps DDR memory support, and 24 10 Gbps SERDES links, RT PolarFire offers huge potential to advance re-configurable on-board digital processing for the space industry.
Radiation testing of RT PolarFire has confirmed a total-dose tolerance greater than 300 krad (SiO2) on its complementary SONOS configuration cell. The push-pull design improves long-term storage retention and performance over time and temperature.
SEE testing was performed on the configuration logic, the D-type flip-flops within the fabric, the µSRAM, and LSRAM. No configuration upsets were detected and the GEO error rates at solar min with 100 mils of Al shielding are 4.44×10-8 and 9.21×10-8 upsets/device/day for the µSRAM and LSRAM respectively. Single-error correction and double-error detection (SECDED) EDAC of the LSRAM embedded memory was not enabled.
For the fabric flip-flops, the GEO error rate at solar min with 100 mils of Al shielding ranged from 3.36×10-8 to 4.44×10-8 upsets/device/day based on the test pattern. Triplication was not implemented.
To make your designs more robust, one can manually triplicate the logic within the HDL or automatically within Libero SoC, as well as enable SECDED protection of the LSRAM embedded memory.
SEL sensitivity depends on applied voltage and temperature: at 100°C with the I/Os biased at 3.465V (3.3V + 5%), SEL was detected at LET levels of 48 MeV-cm2/mg. At 100°C with the I/Os biased at 2.625V (2.5V + 5%), no LET was detected at LET of 63 MeV-cm2/mg. SEL was detected at 68.5 MeV-cm2/mg, therefore the measured LET threshold is between 63 and 68.5 MeV-cm2/mg. When tested at 100°C with I/Os biased at 1.89V (1.8V + 5%), no SEL was detected up to 82.1 MeV-cm2/mg.
Radiation testing of the PLL, SERDES, clock networks, triplication of the fabric D-type flip-flops, as well as the embedded memories with EDAC enabled (hard IP for LSRAM and soft for µSRAM) is planned over the next few months and I will provide a further update once these results become available.
Mil Std 883 class B, QMLQ and QMLV-qualified devices will be available in hermetically-sealed, ceramic 1509 CGA and LGA packages with 1 mm pitch.
Figure 2 This diagram shows the functional blocks of the RT PolarFire FPGA.
The following table compares the specification of RT PolarFire with competing ultra deep-submicron space-grade FPGAs. I will be continuing this comparison at ESA’s FPGA conference which will be re-scheduled at ESTEC.
Figure 3 Compare the ultra deep-submicron space-grade FPGAs from various companies.
Low-cost versions of the commercial PolarFire devices are available with fewer logic resources, from 100 to 500k logic elements, and plastic packages as small as 11×11 mm as listed below. These contain the same silicon design as RT PolarFire, which is interesting for NewSpace satellite/spacecraft OEMs.
Figure 4 Comparison of commercial-grade PolarFire FPGAs.
Spacechips teaches and compares RT PolarFire with competing ultra deep-sub-micron space-grade PLDs on its FPGA training course. Until next month, the first person to tell me why older floating-gate switches are sensitive to total dose radiation will win a Courses for Rocket Scientists World Tour t-shirt. Congratulations to Brian from Singapore, the first to answer the riddle from my previous post.
Dr. Rajan Bedi is the CEO and founder of Spacechips, which provides ultra high-throughput on-board processing and transponder products, design consultancy in space electronics, training, technical-marketing and business-intelligence services. You can also contact Rajan on Twitter.