Does your spacecraft flash?
Article By : Rajan Bedi
A flash FPGA is the ideal digital on-board processing technology for space applications: its non-volatile yet can be re-programmed during prototyping and in-orbit.
A flash FPGA is the ideal digital on-board processing technology for space applications: it’s non-volatile yet can be reprogrammed during prototyping and in-orbit. Your intended functionality, i.e., the configuration, is stored as a charge within a floating-gate transistor, which is immune to radiation upsets.
The non-volatility of flash-based FPGAs avoids the need for an external configuration memory to reboot your intended functionality at power-up. This saves physical space on your PCB, reduces power consumption, and in some cases, eliminates the need for an extra voltage regulator. Overall, the use of a flash-based FPGA rationalises your BOM!
The fabric of flash-based FPGAs differs from hardened SRAM devices and, fundamentally for space-grade parts, requires significantly fewer transistors to store each bit of configuration data, e.g., 12 vs. 2. Hence for the same geometry, flash-based FPGAs consume less power. The resulting finer granularity within a flash fabric allows for very high logic utilisation, enhancing routing and performance.
Late last year, Microsemi announced that it will be offering a 352-pin, CQFP version of its 65 nm RTG4 FPGA. I’m really intrigued by this latest part as it offers the space industry the performance and power-consumption advantages of 65 nm ultra-deep-submicron technology if you do not actually need 720 I/O. The CQ352 contains the same die as the original RTG4150-1xx1657, but has been placed in a more ‘user-friendly’ package, which satellite manufacturers traditionally find easier to assemble and mount. 166 I/O and 4 high-speed serial links are available.
Figure 1 The original 1657-column RTG4 and its new 352-pin CQFP variant
The RTG4 rad-hard FPGA contains 151,825 logic elements each containing a TMR flip-flop and an SET filter. Its user memory supports SECDED EDAC and logically-adjacent bits have been interleaved in the physical layout to protect against multiple-bit upsets. The device has been fabricated on a bulk 65 nm process with an epitaxial layer to mitigate latch-up. Compared to previous space-grade flash devices, the design of the floating-gate switch/cell used to connect two routing tracks or a signal to an input or output from a logic element has been improved: the RTG4 implements an indirectly-coupled interconnection scheme offering a total-dose tolerance > 100 kRad (Si) without incurring an increase in propagation delay or loss of functionality.
The table in Figure 2 compares the specification of both parts. The significant differences between the devices are that the new CQFP version contains less I/O and fewer high-speed serial links.
Figure 2 Specifications of 1657-column and 352-pin, RTG4 flash FPGAs
As the rad-hard die are identical, the raw processing performance remains the same: for the new 352-pin device, in absolute terms, I/O and SERDES consume relatively small amounts of power reducing as a percentage of the overall dissipation as a function of logic utilisation. Figure 3 shows predictions calculated by Microsemi’s power estimator spreadsheet based on a system clock of 300 MHz and a toggle rate of 12.5%. The solid lines plot total device consumption for different I/O formats with respect to the left y-axis, while their dashed equivalents show the proportion due to I/O with respect to the right y-axis. The majority of power is dissipated by the logic, clock, and maths blocks.
The traces prefixed with ‘1657’ plot the predicted device consumption for the larger 1657-column part using all of its 720 I/O. When using LVCMOS25, the total dissipation is only less than or equal to 0.5% higher than the equivalent 352-pin part. With LVDS signalling, there is a larger increase in power consumption, from 22 to 8% as a function of logic utilisation, and the proportion attributable to I/O shows a more marked rise.
Figure 3 RTG4 total device power consumption and I/O contribution
Libero SoC 11.8 is required to implement designs on both RTG4 devices and Microsemi’s power estimator version 4A to provide early power-consumption predictions.
The advantages of a 65 nm flash FPGA, now available with reduced I/O count and a more accessible package, opens up interesting new mission possibilities for the RTG4 family. Microsemi recently announced that the 1657 CGA/LGA versions have successfully completed QML Class Q qualification, the SMD has been approved, and Class V certification is expected later this year.
I will be presenting free tutorials on space electronics at Space Tech Expo in Pasadena, CA on the morning of Wednesday 23rd of May; in Madrid, Spain on Monday 11th of June; and in Toulouse, France on Wednesday 13th of June. Please email events@spacechips.co.uk for further details and to register.
Until next month, the first person to tell me why older floating-gate switches are sensitive to total dose radiation will win a Courses for Rocket Scientists World Tour t-shirt. Congratulations to Tim from Scotland, the first to answer the riddle from my previous post.
Rajan Bedi is the CEO and founder of Spacechips, which provides on-board processing products, design consultancy in space electronics, technical-marketing, training and business-intelligence services.
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