Drag and drop with new software and IP for processor-based FPGA design

Article By : Nitin Dahad

A new design environment to empower developers of any skill level to quickly design FPGA-based applications using a drag-and drop graphical user interface...

In order to utilize the parallel processing capabilities of FPGAs in more complex systems, FPGA developers need to be able to implement designs with processor, relevant intellectual property (IP) and software without requiring detailed RTL knowledge or expertise.

To address this need, Lattice Semiconductor has introduced a new design environment to empower developers of any skill level to quickly design Lattice FPGA-based applications using a drag-and drop graphical user interface to easily assemble components from an IP library that includes a RISC-V processor core and a number of peripherals. Its’ Propel design environment – which combines two tools, Lattice Propel Builder (for IP system integration) and Lattice Propel SDK (for application software development) – automates application development for developers serving the communications, computing, industrial, automotive, and consumer markets.

The Lattice Propel design environment comprises a GUI-based Builder and an SDK (Image: Lattice Semiconductor)

The design software, Propel Builder, is a system IP integration environment supported by a complete set of GUI and command line tools. It provides customers with access to a regularly updated IP server that allows developers to implement new IP on Lattice FPGA-based designs in a matter of minutes. As of launch, the server currently offers eight processor and peripheral IP cores, including a RISC-V RV32I compliant processor core. Lattice said it is the first supplier of SRAM and Flash-based FPGAs to provide access to RISC-V technology in a simple drag-and-drop system builder environment.

For novice FPGA developers, IP blocks from the Lattice IP library can be dragged and dropped in place into their designs; the tool then automates the design layout to incorporate the new IP. For veteran developers, Propel also supports script-level editing for more granular design optimization or to quickly update existing designs to port them to future Lattice FPGA-powered systems. To simplify the connection and management of IP in more complex systems, IP cores available through Propel Builder are compatible with the AMBA on-chip interconnect specification.

The drag and drop user interface in Propel Builder can be used by novice as well as experienced FPGA developers (Image: Lattice Semiconductor)

For designs implemented in the Propel design environment, the Lattice Propel SDK enables software development to begin before final system hardware is available. The Propel SDK includes industry-standard software development tools, software libraries, and development board support packages so developers can quickly and easily build, compile, analyze, and debug their application software.

Lattice said the Propel design environment supports open standards like RISC-V to enable customers to take advantage of a powerful processor IP ecosystem without getting locked into proprietary technologies and standards. When combined with the reprogrammability of FPGAs, Propel makes it simple to upgrade existing hardware and software to support emerging technology trends and industry standards such as platform firmware resiliency.

At launch, Propel is supporting the Lattice MachXO3D FPGA for secure system control, and will be adding support for other FPGAs targeting edge AI and smart vision applications in the future.

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