Why you should always follow switch-mode power layout guidelines

Article By : Syafiqa Zupli & Mohamed Ismail

Just like children should listen when parents tell them to eat their vegetables, engineers should follow layout guidelines when semiconductor manufacturers recommend them.

Open any switching power-supply datasheet or design handbook and the message is the same: follow these layout guidelines, OR ELSE. Even if the schematic has all the proper connections and the bill of materials (BOM) has components rated for the application, many power-supply designs are doomed to fail due to poor layout. When troubleshooting a design that ‘should work,’ most problems can be traced back to the layout guidelines found in these handbooks and datasheets. Just like children should listen when parents tell them to eat their vegetables, engineers should follow layout guidelines when semiconductor manufacturers recommend them. For a simple buck converter, some of these guidelines include:

  • Placing the input capacitor as close to the chip input as possible. When the high-side FET turns on, input capacitors deliver a high di/dt current pulse. Placing input capacitors close to the IC minimizes parasitic inductance between the input capacitors and high-side switch. This results in a lower voltage drop across the parasitic inductance (i.e. V=Ldi/dt).
  • Keeping high-current paths as short and wide as possible. This will decrease trace inductance and resistance in high-current paths, which may significantly increase efficiency in high-current applications.
  • Minimizing the loop area formed by the inductor switching node, output capacitors, and input capacitors. This helps keep high-current paths short and wide, and it also reduces the radiated electromagnetic interference (EMI) that may affect nearby components (including the power supply’s feedback and compensation components).
  • Routing high-speed switching nodes away from sensitive analog areas. If possible, keep the feedback resistors, compensation network, and soft-start capacitor (if used) outside of the high-current loops and as close to the IC as possible.
  • Placing a GND plane immediately below all power components and traces carrying high switching currents. Doing so will reduce parasitic inductance. The top layer and second layer are ideal for GND plane placement so it can shield signals in other layers from the power-switching waveforms.
  • If there is an exposed paddle, use multiple vias to connect it to the GND plane. Using as many vias as possible will increase both the thermal conductivity and electrical conductivity between the exposed paddle and GND plane, which will keep the IC cool and increase efficiency.

It’s one thing to know the recommendations; it’s another thing entirely to follow them. Unlike parents, who sometimes struggle to demonstrate the immediate benefits of eating vegetables to their kids, engineers can immediately demonstrate the consequences of poor power-supply layout to their bosses. To experience the effects of breaking each of these rules ourselves, we intentionally built boards that disobeyed the recommendations and characterized each one.

Quick and reliable power-supply design
To start our design, we named a general-purpose step-down application:

  • +12V (+/-2%) input voltage
  • +3.3V output voltage
  • 0.1V load transient overshoot/undershoot maximum
  • 5A maximum output current
  • balance of efficiency and size

Since the intent of this design was to examine the effects of different board layouts, we needed to produce a well-designed schematic with appropriate component ratings (and de-ratings), a BOM with all orderable components, and a circuit we could simulate to compare the achieved performance versus the expected values. To generate a new design as quickly as possible, with all of the above capabilities, we used Maxim’s EE-Sim design tool. We entered our input/output specifications and generated final simulation results with an orderable BOM. After entering the schematic into our CAD program, we had the circuit based on the MAX17506 step-down converter (Figure 1).

Figure 1 Final design for +3.3V, 16.5W step-down converter

To investigate different layout considerations, we built one ‘optimized’ board to compare with the simulation results and serve as our scientific control and five ‘variant’ boards that each disobeyed one of the rules listed above.

Board #1 – Optimized layout
The first optimal board layout is shown in Figure 2, with the top layer in red, second layer in orange, third layer in green, and bottom layer in blue. Note that:

  • The input capacitors (C101, C102) are next to the input pins.
  • The input path, output path, and LX node are all top-layer planes to minimize impedance.
  • The input capacitors (C101, C102), output capacitors (C108, C109, C110), and inductor (L101) are adjacent to each other to minimize the conduction loop.
  • The feedback components (R103, R104, C112), frequency-setting resistor (R105), and soft-start capacitor (C107) are placed below the control IC, away from the high-current paths placed above the IC.
  • There are layers upon layers of GND planes (way more than necessary) to help with high-current conduction.
  • The exposed paddle is connected to the internal GND planes through nine vias.

Figure 2
Optimal layout of the MAX17506 buck converter design

When the time came to validate the optimal layout versus the simulation results, the board was tested for efficiency, output voltage ripple, load transient performance, and the switching-node waveform. These results were compared to the original EE-Sim simulation results to judge how well the board was designed.

Efficiency: Simulation versus optimized layout
Perhaps the most scrutinized specification when evaluating any power converter’s performance is its efficiency, or how well the converter transfers the input power to the output. After verifying that the board turned on successfully, power efficiency was the first comparison made between simulation and bench data. Figure 3 shows the comparison of the expected versus achieved efficiencies.

Figure 3 Simulation versus measured efficiency

Overall, the optimized board produced similar results to the EE-Sim efficiency simulation. The achieved efficiency was ~4% higher at a lighter load of 500mA, but ~1% lower at a full load of 5A. This established a good baseline to compare with the non-recommended layouts.

Load transient: Simulation versus optimized layout
Another heavily scrutinized performance benchmark for a power converter is how it responds to transient changes in the load current. These waveforms are also used to indirectly measure a converter’s stability, as loop stability measurements require specialized equipment that may not be available. In our design parameters, we specified 0.1V maximum overshoot/undershoot, and Figure 4 shows the simulated load transient response versus the achieved response.

Figure 4 Simulated load transient response (left) versus achieved response (right).

In the simulation, a load step from 2.5A to 5A yielded a 70mV undershoot in output voltage that recovered within 190us, and the measured response yielded an 80mV undershoot that recovered within a 180us. When the load dropped from 5A to 2.5A, the simulation showed a 70mV overshoot that resolved in 180us and the measured response showed an 80mV overshoot that resolved within 180us. This near-perfect match in simulation and characterization inspired confidence in the layout of our first board.

Output voltage ripple: Simulation versus optimized layout
The output ripple of a converter depends on many factors, including the output capacitor equivalent series resistance (ESR), feedback network placement, load current, etc. Since we specified a 0.1V maximum overshoot/undershoot in our design, the voltage ripple for a static load current was expected to be much smaller. Figure 5 shows the simulated output voltage ripple given a 2.5A load, as well as the measured ripple on our optimized layout board.

Figure 5 Simulated (left) versus measured (right) output ripple with 2.5A load

The simulated output voltage ripple was 5.2mVPP, and the measured output ripple was closer to 10mVPP. Additionally, while care was taken to minimize the measurement loop from the output to our oscilloscope probe to GND, there is still some expected switching interference coupled into the output voltage waveform due to the ESL effect of the capacitor.

Switching-node waveform: Simulation versus optimized layout
In the design, we configured the MAX17506 for a fixed frequency of 313kHz in pulse-width modulation (PWM) mode. Thus, for a static load current, the switching node should appear to be a square wave switching between GND and +12V with a near-constant duty cycle. Figure 6 shows the simulated and measured switching-node waveforms.

Figure 6 Simulated (left) versus measured (right) switching-node waveforms

With a target frequency of 313kHz, the expected switching period was 3.2us. For 2.5A, the switching waveform in the simulation showed a 3.4us period and 1.1us on-time, and the measured switching waveform showed a 3.1us period and 0.9us on-time.

After comparing the efficiency, voltage ripple, load transient response, and switching node waveform of our initial design with the ‘optimal’ layout to the simulation results from EE-Sim, we established a baseline in-lab performance to serve as the basis of our layout study.

[Continue reading on EDN US: Board #2 – No exposed paddle vias to GND plane]

Syafiqa Zupli is an associate member of technical staff at Maxim Integrated.

Mohamed Ismail is an electrical engineer at Synapse Product Development.

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