Mentor has broken with the mould in announcing a 5-year roadmap for the VeloceStratoM platform, which holds 64 verification boards and consumes 22.7W/Mgate when fully loaded.
Mentor Graphics has rolled out its VeloceStratoM, an emulation platform that the company says supports a roadmap to 2022, when it will be capable of handling chip designs with 15 billion gates, consequently breaking with EDA’s standard procedure.
“This is not a typical EDA announcement, because we are announcing a platform that basically will carry over for five years,” said Jean-Marie Brunet a senior director of marketing at Mentor, in an interview with EE Times. “We aren't going to come back in two years and say, 'Forget what we said in 2017, here's a new platform.' Everything that we are going to do for the next four to five years is around that VeloceStratoM platform."
Emulation is a bit different than the rest of EDA wherein it relies on a very costly hardware component. According to Brunet, advanced CPUs, GPUs, CPU and GPU combinations and network processors feature about 1.5b gates. By 2022, Mentor expects that number to increase tenfold to reach 15b gates.
Figure 1: According to a Mentor spokesperson, advanced CPUs, GPUs, CPU and GPU combinations and network processors feature about 1.5b gates. By 2022, Mentor expects that number to increase tenfold to reach 15b gates.
The VeloceStratoM has available slots for 64 advanced verification boards and consumes up to 50kW (22.7W/Mgate) of power when fully loaded, according to Mentor. The company claims performance improvements over previous generation systems including total throughput up to 5x (fastest compile-runtime-debug sequence), time to visibility up to 10x, compilation time up to 3x and co-model bandwidth up to 3x.
The VeloceStratoM is already in use by chip companies, Brunet said. The emulator is capable of 2.5b gate capacity when fully loaded and the total capacity increases as the number of emulators are connected together via Mentor’s VeloceStrato link, he said.
The emulation platform is aimed initially at the most advanced chip designs. But because it is scalable, Brunet said companies that are designing chips with fewer gates are already looking at it for the future.
“We are looking at the high end,” he said. “We are not looking at the small IoT guys that are around 65nm. We are looking at, as of today, who is in 2017 the leading edge in terms of size. Because those high end customers in size, they are the ones driving the ecosystem in our industry.”
Brunet said Mentor has been guilty of not communicating much about its emulation roadmap in the past. Mentor tends to be a conservative company when it comes to making claims about product performance and capability, he said.
"By the nature of being more conservative, customers feel like you don't really have a roadmap," he said. "Well, we do have a roadmap, and that's what we are changing. We feel so comfortable with what we have here that we are going to talk about the roadmap.”
First published by EE Times.