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This imaginative design eliminates ripple and greatly speeds a PWM DAC using only a few components.

The enduring simplicity of PWM DACs will always earn them a place in the designer’s cookbook, but slow response time and the problem of PWM ripple tend to limit their appeal and utility. The usual way of attenuating PWM ripple, an RC low pass filter, can never succeed in completely eliminating it, and only makes output settling time agonizingly slow if you try. **Figure 1** shows a different approach, which can overcome these drawbacks – using a synchronous S&H (sample & hold).

The **Design Idea** relies on the inherently periodic nature of PWM ripple, which makes it have exactly the same voltage at any synchronously chosen point in the V_{C1} waveform, as shown in **Figure 2**. Therefore, if V_{C1} is synchronously sampled, as by Figure 1’s analog switch S1 and transfer capacitance C2, then held (hence Sample-and-Hold) to produce output V_{out} as by C3, the result will be a smooth, ripple-free V_{out} regardless of how large the AC component at V_{C1} might be. This is illustrated in the plots of DAC dynamic behavior in Figure 2.

Moreover, because synchronous sampling inherently eliminates ripple independent of how short the RC1 time constant may be, it follows that the RC1 product can be made quite short indeed. This can dramatically cut settling time, as in Figure 1, where RC1 = 100 µs = T_{c} = the PWM period, resulting in settling (to 8-bit precision) in less than 15·T_{c} = 1.5 ms for the example case. But of course, as with all good things, we know there must a limit. So the question becomes: How short can RC1 be made consistent with proper DAC function, and what design factors set that limit?

A closer look at the V_{C1} waveform suggests the answer: V_{out} is sampled, not from the average value of V_{C1}, but from the the ripple maxima. Therefore:

With…

Summing this non-linear component with the DAC V_{out} function therefore makes the DAC transfer function nonlinear too, resulting in an integral nonlinearity (INL) error that, with the example circuit constants, can be as large as 8.3% of full-scale. For many applications, this much INL would be unacceptable. Fortunately, there’s a simple (software) fix: Numerical pre-emphasis of the DAC setting. For example, using the constants of Figure 1, where…

If we alter T_{p }…

The V_{ripple} term will disappear from V_{out} and 8-bit INL is restored.

It’s worth mentioning the “optional” elements V_{s} and S2 which generate the RC1 input waveform from a precision reference (V_{s}), and thus avoid superimposing the noise and dodgy regulation often characteristic of logic power supplies (and therefore riding on the PWM logic signal) on V_{out}. Of course if the accuracy requirements of your application are sufficiently undemanding to make this unnecessary, they can be omitted, and R simply connected directly to the PWM signal.

Worth mentioning because, as I said at the outset, enduring simplicity *is* one of the main charms of PWM DACs!

**Related articles**:

- A faster PWM-based DAC
- Cancel PWM DAC ripple with analog subtraction
- Fast-settling synchronous-PWM-DAC filter has almost no ripple
- Hybrid PWM/R2R DAC improves on both
- Three paths to a free DAC
- Double µC’s PWM frequency & resolution
- Combine two 8-bit outputs to make one 16-bit DAC
- Pulse-width modulation
- Circuit maximizes pulse-width-modulated DAC throughput

—*W. Stephen Woodward** is one of EDN’s most prolific and innovative Design Ideas authors, with dozens of contributions to his credit.*