Four things to know about the Intel Pathfinder for RISC-V

Article By : Majeed Ahmad

Here are key technical aspects and chip designer takeaways of the Intel Pathfinder for RISC-V initiative.

As if Intel testing the RISC-V waters wasn’t news in itself, the semiconductor behemoth’s Intel Pathfinder for RISC-V initiative is now making the headlines. RISC-V is an open standard instruction set architecture (ISA) that offers chip developers the freedom to configure a custom processor with standard extensions and configuration options.

Vijay Krishnan, general manager of RISC-V Ventures at Intel, acknowledges that the adoption of RISC-V is at an inflection point across multiple markets and applications. Intel, which spearheads the x86 ISA world, has been proactive in the RISC-V space for quite some time. Now, its Pathfinder platform is promising to bolster the RISC-V design ecosystem for developing and prototyping chip designs with robust software and industry-standard toolchains.

Source: Intel

This blog summarizes the key technical aspects and IC designer takeaways of this Intel initiative.

  1. Two Pathfinder versions

Intel Pathfinder is initially available in two versions: Starter Edition and Professional Edition. Starter Edition—intended for the hobbyist, academia, and research community—is available as a free download. Professional Edition, which comes with broad ecosystem support, targets firms involved in developing commercial silicon and software.

For instance, it includes fixed platform kits (FPKs) from Imperas to offer delivery of pre-configured platform models as a binary installation without licensing management or complex installation set-up.

  1. Intel Stratix FPGAs

The initiative is built around Intel’s Stratix FPGAs and FPGA boards for developing and prototyping system-on-chips (SoCs) based on the RISC-V processor platform. FPGAs have been an essential part of the IC design value chain in the prototyping and production stages. Here, Intel FPGAs come with software tools like Intel Stratix 10 GX FPGA Development Kit, which allows chip designers to boot Linux OS or upload compute kernels to the FPGA board during the pre-silicon development.

  1. Cores and IPs

Intel Pathfinder will allow a variety of RISC-V cores and other IPs to be instantiated on FPGA and simulator platforms. And it will do so while IPs utilize prominent operating systems and toolchains within a unified integrated development environment (IDE). That, in turn, saves time in assembling and testing different IP combinations in a single design environment.

Exploring different configurations and combinations of IP in the early stages of the SoC development cycle is highly beneficial. For example, Codasip is making its 32-bit L31 core available through the Professional Edition of the Intel Pathfinder for RISC-V program.

Intel Pathfinder provides a common environment for accessing RISC-V and peripheral IP on its FPGA boards. Take the case of Andes Technology, which has ported its 512-bit vector processor core NX27V and 64-bit superscalar multicore AX45MP to the Intel Stratix 10 GX FPGA board.

  1. Software toolchains in a unified IDE

With Intel Pathfinder, the Santa Clara, California-based chipmaker is embracing a software-first development approach. That encompasses a unified IDE, software toolchains and commonly used operating systems, essential ingredients for embedded software developers. Then there are reference models for hardware verification use cases such as compliance, verification and test development as well as software development targets for firmware, drivers, OS porting, and application development.

Intel Pathfinder, for example, includes a reference model to provide the simulation environment that supports bare metal or applications with operating systems like Linux or RTOS as a starting point. Also, there is Imperas simulator with proprietary just-in-time code-morphing simulation technology. It can be integrated within other standard EDA environments such as SystemC and SystemVerilog as well as well-known simulation/emulation tools from Cadence, Siemens EDA, and Synopsys plus the cloud-based offering from Metrics Technologies.


This article was originally published on EDN.

Majeed Ahmad, Editor-in-Chief of EDN and Planet Analog, has covered the electronics design industry for more than two decades.


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