Samsung's development of the 3nm gate-all-around (GAA) process is on track and it has already made available the PDK in April this year.
Samsung Electronics has announced that its development of the 3 nm gate-all-around (GAA) process called 3GAE is on track and that it has made available version 0.1 of its process design kit (PDK) in April this year. Samsung is adopting the GAA architecture for 3-nm process nodes to overcome the physical scaling and performance limitations of the FinFET architecture.
Samsung’s fab executives are quick to point out that the conventional GAA based on nanowire—also known as GAAFET—requires a larger number of stacks due to its small effective channel width. On the other hand, Samsung’s multi-bridge-channel FET (MBCFET) technology uses a nanosheet architecture to enhance gate control. That, in turn, enables greater current per stack.
Figure 1 The process node evolution marks a fundamental shift in how chips are manufactured. Source: Samsung
Another key distinction: the existing FinFET structures must discretely modulate the number of fins. Here, MBCFET provides greater design flexibility by controlling the nanosheet width. Samsung claims that its first 3-nm GAA process node utilizing MBCFET will allow up to 35% decrease in area, 30% higher performance, and 50% lower power consumption than the 5-nm process. Moreover, the logic yield of 3 nm is approaching a level similar to the 4-nm process, which is currently in mass production.
Samsung’s fab operation is scheduled to start producing its first 3 nm chip designs in the first half of 2022 and its second generation of 3 nm chips in 2023. Next in Samsung’s technology roadmap is the 2-nm process node with MBCFET; it’s in the early stages of development with mass production targeted in 2025.
TSMC, Samsung’s arch-rival in contract manufacturing of chips, also claims that its development of 3 nm process node is on track, and it’s targeting volume production in the second half of 2022. It’s important to note that TSMC is using the FinFET transistor structure for its 3 nm process node, and that means semiconductor companies won’t require new EDA tools and the development of new IPs.
However, Samsung executives point out that MBCFET’s compatibility with FinFET processes means that engineers can employ the same manufacturing technology and equipment for these two technologies. That, in turn, will accelerate the process development and production ramp-up.
Figure 2 Samsung has taken the lead over TSMC in implementing the GAA technology at 3 nm process nodes. Source: Samsung
TSMC will start employing the GAAFET technology for its 2-nm processor nodes. So, Samsung, which is still far behind TSMC in market share, has taken a big technology risk by moving to the GAA technology one generation ahead of the Taiwan-based mega fab.
Samsung is already developing initial design tools along with partners and has unveiled its process technology migration plan to GAA-based 3 nm nodes at its 5th annual Samsung Foundry Forum (SFF) 2021. The Korean giant is known for making the right technology bets and defying the common business wisdom. It’ll be interesting to watch how Samsung’s GAA gamble pays off in its mega-fab business rivalry with the world’s largest contract maker of chips.
This article was originally published on EDN.
Majeed Ahmad, Editor-in-Chief of EDN, has covered the electronics design industry for more than two decades.