Fundamentals of I3C interface communication

Article By : Robert Perkel, Microchip Technology Inc.

I3C brings a significant increase in the bandwidth of the serial bus while adding a slew of new features like hot-join, IBI, and HDR modes.

I3C is a new serial communication protocol for embedded systems that offers significantly higher data throughput and more advanced features than I2C. With I3C, engineers and designers can improve the performance of their designs while also adding in new features like hot-join, in-band interrupts (IBI), and high data rate (HDR) modes. Additionally, I3C is backward compatible and can communicate with legacy I2C targets. Table 1 summarizes the differences between I3C and I2C.

Table 1 The above data demonstrates how I3C offers significantly higher data throughput and more advanced features than I2C. Source: Microchip


  1. Nominal values. Other values are not disallowed.
  2. Clock stretching can be performed by the active controller (not the target) with restrictions on timing and bus state.
  3. HDR is not required for basic I3C communication. I3C buses support HDR communication even when non-capable devices are connected. See high data rate (HDR) modes for more information.

Bus speed

The most noticeable change between I2C and I3C is clock speed. I2C is usually 100 kHz, 400 kHz or 1 MHz, whereas I3C can reach speeds up to 12.5 MHz. One of the main factors for this increase is the use of push-pull outputs in I3C. I3C switches between open-drain and push-pull drivers depending on the bus state. Open-drain is used during initial addressing or arbitration where multiple targets may control the line at the same time. In contrast, push-pull is used when communication is unidirectional, and there is no chance of another device communicating at the same time.

Electrical characteristics

Unlike I2C, I3C does not require external pull-up resistors, as the main controller on the bus provides these functions. I2C has a wide operating range, with 3.3 V and 5 V being the most common. I3C has three nominal levels: 1.2 V, 1.8 V, and 3.3 V. However, other operating ranges are allowed.

Device addressing

I2C supports 7-bit and 10-bit addressing of target devices. With I3C, only 7-bit addressing is supported. However, I3C uses dynamic addressing, where the active controller assigns each target a unique address to prevent address collision. This contrasts with I2C, where developers must keep track of the currently used addresses to prevent two devices from sharing the same address. Dynamic addressing of targets happens during bus initialization.

In-band interrupts and hot-join

In I2C, there is no mechanism for a target to indicate to the controller that data is ready without using an extra I/O line. But in I3C, target devices may signal an interrupt using the serial data (SDA) and serial clock (SCL) lines, thus making it a true two-wire protocol. Likewise, this type of in-band signaling is also used to implement hot-join functionality in I3C, so devices can join after the initial address assignment. The in-band interrupts (IBI) and address arbitration section will discuss this in more detail.

Active and secondary controllers

I2C supports multi-controller buses, where multiple devices operate as controllers, but only one is actively communicating at a time. However, in I3C, only one device can be the active controller; other capable devices may request to become the active controller on the bus. Such a device is known as a secondary controller. When a secondary controller is not acting as the active controller, it functions as an I3C target.

I2C support

I3C supports communication with I2C target devices. For communication to be possible, the I2C targets must:

  • Have a 7-bit address
  • Does not clock stretch

It’s also strongly recommended that the I2C target contains 50-ns filters on its inputs. If these requirements are met, then the I2C target is compatible with the I3C bus. Additionally, some I3C devices can operate as an I2C target until assigned a dynamic address. While in I2C mode, the I3C device has a static address for communication. This static address is not necessarily the same as the dynamic address, but it can be assigned the same, if desired. An example of an I3C bus is shown below.

Figure 1 The diagram highlights an I3C bus. Source: Microchip

Basics of I3C communication

Before any communication can begin on an I3C bus, the bus must be configured, and dynamic addresses must be assigned to the targets.

Then, communication begins like I2C. A START condition is generated, then a 7-bit dynamic address is sent, with an R/nW bit followed by an ACK or NACK from the target. Next, I3C uses 9-bit serial transfers like I2C, but the function of the 9th bit has been changed from ACK/NACK to a Transition bit, or T-bit. The T-bit has two functions; when the controller is writing to a target, the T-bit is an odd-parity bit of the data byte sent. When a controller is reading from a target, the T-bit is used as an End-of-Data flag. This flag can be asserted by either the controller, to signal that it’s done reading data, or by the target, to signal that it has no more data to return. To complete the data transfer, the controller generates the STOP or RESTART condition on the bus. Note, if a RESTART is used, the header is transmitted in Push-Pull since there is no arbitration.

Figure 2 A simplified diagram of data transfer in I3C is shown with 1 data byte. Source: Microchip

A crucial change with I3C is the lack of clock stretching. I2C uses clock stretching to give target devices more time to process before returning data. With I3C, the clock is only driven by the active controller—in single data rate (SDR) mode. Therefore, clock stretching can only be performed by the controller under limited circumstances.

However, the target device can indicate speed restrictions during the bus initialization process to indicate a maximum operating frequency, read and write turnaround times, and other timing parameters.

Common command codes (CCC)

Common command codes (CCC) are a new concept in I3C. CCCs are used by the active controller to initialize and/or configure the I3C bus. CCCs can be broadcast to every target or can be directed at a specific target privately. To send a CCC, first, send the address 7’h7E/W. All I3C devices must acknowledge and listen to this address. I2C devices cannot match this address, as 7’h7E is reserved per the I2C specification. Next, send the CCC code. For CCCs that write data to targets, continue sending data until complete. For CCCs that read values, send any parameters (as needed), restart the bus, and begin reading data.

There are too many CCCs to discuss, but here is a selection of important ones:

Enter Dynamic Address Assignment (ENTDAA)

Enter Dynamic Address Assignment notifies all targets that the active controller is assigning dynamic addresses. If a target is already assigned an address, it will NACK this command.

Set New Dynamic Address Assignment (SETNEWDA)

Set New Dynamic Address Assignment is used to change the dynamic address of a device.

Enable Events (ENEC)/Disable Events (DISEC)

Enable or Disable Event commands indicate whether events like hot-join or in-band interrupts are currently allowed on the bus.

Reset Dynamic Address Assignment (RSTDAA)

Reset Dynamic Address clears the currently assigned address but does not reassign one. In v1.1 of the I3C specification, the direct form of the Reset Dynamic Address Assignment has been deprecated.

Set Max Read Length (SETMRL)/Get Max Read Length (GETMRL)

Set or Get Max Read Length specifies the maximum number of bytes that can be read at a time.

Set Max Write Length (SETMWL)/Get Max Write Length (GETMWL)

Set or Get Max Write Length sets the maximum number of bytes that can be read or written at a time.

Get Device Characteristics Register (GETDCR)

The Device Characteristics Register, or DCR, is a register that specifies what kind of device the target is. An example of this would be code 0xC6, the code for a microcontroller. The I3C specification defines DCR values. A list of these codes is available from the MIPI Alliance.

Get Bus Characteristics Register (GETBCR)

The Bus Characteristics Register, or BCR, is a register that defines what I3C capabilities are present on the target. This register is also used to determine whether a speed restriction is necessary for the target.

Target Rest Action (RSTACT)

The Target Reset Action in CCC defines what happens to targets when the in-band reset pattern is detected. To generate a reset, SDA is held low while SCL is clocked 14 times, followed by a Restart and then a STOP. Targets detect the in-band reset pattern and act according to what they were assigned. This CCC does NOT trigger a reset but assigns the target behavior. If not reset following this command, the next START condition will clear the assigned action.

Enter High Data Rate Mode (ENTHDRx)

Finally, there is the high data rate, or HDR, Entry CCC. This CCC indicates that the active controller is entering one of the four HDR modes (0, 1, 2, or 3).

High data rate (HDR) modes

There are four HDR modes currently defined by the I3C Specification.

  • HDR double data rate (HDR-DDR) [Mode 0]
  • HDR ternary symbol pure-bus (HDR-TSP) [Mode 1]
  • HDR ternary symbol legacy-inclusive-bus (HDR-TSL) [Mode 2]
  • HDR bulk transport (HDR-BT) [Mode 3]

While in HDR, the clock rate doesn’t change the way data is encoded changes. HDR is not required for I3C basic communication. Devices that don’t support HDR ignore communication until they detect the HDR exit pattern.


HDR-DDR is a mode that uses both edges of the clock to transmit data. This significantly increases the data rate of the bus (but does not double it due to extra overhead in the protocol).


In HDR-TSP and HDR-TSL, data is transmitted in ternary, with three defined symbols created from the SDA and SCL lines. From the specification, the symbols are electrically defined by:

  • Only SCL changes
  • Only SDA changes
  • Both SCL and SDA changes

The choice between HDR-TSP and TDR-TSL is based on whether an I2C target is present. HDR-TSP can only be used when I3C targets are present, whereas HDR-TSL is used when a legacy I2C target is present.


HDR-BT allows for multiple data lanes to be used at the same time for more parallelism. For compatibility, only the least significant bit, or LSB, of the SDA line is used for single data rate (SDR) communication. HDR-BT supports dual- and quad-line configurations. Figure 3 shows an example configuration.

Figure 3 The diagram provides an example of a mixed I3C bus with HDR-BT support. Source: Microchip

In-band interrupts (IBI) and address arbitration

Unlike I2C, targets can generate the start condition for IBI when the bus is idle (or free). This happens if no transactions occur for a certain length of time. When the active controller detects the start condition from the target, it provides the clock signal to complete the transaction. If two targets attempt to communicate simultaneously, addressing arbitration will occur.

Arbitration is the process of determining which device is allowed to communicate with the controller. For example, assume two devices, A and B, would like to talk to the active controller simultaneously. Device A has an address of 7’h10, while device B has an address of 7’h14. When an in-band interrupt is generated, both devices will attempt to transmit their address to the active controller. In this bus state, the data-line is open-drain. During open-drain communication, the line passively returns to “1” through a pull-up resistor and can be actively asserted to “0”. This prevents a short circuit from two devices transmitting 1 and 0 at the same time.

Figure 4 A simplified view of the SDA line shows how the pull-up resistor is built in the main controller. Source: Microchip

The winning address in arbitration is the one that the controller receives. Following along with Figure 5, first, the two zeros are transmitted from each device address. Next, both will release the data line for the “1” in their address. Then, another 0 will be transmitted by both. At this point, neither device has won arbitration, as the address received matches both at this point. But, with this next bit, one of the targets will release the data line to send a “1” while the other attempts to send a “0”.

Figure 5 The example shows I3C arbitration with addresses 7’h10 and 7’h14. Source: Microchip

The transmitter of the “1” will lose arbitration because the “1” is driven passively by the open-drain configuration, while the other target actively asserts the “0”. Completing the rest of the transmission sequence, you can see the controller received the address 7’h10, not 7’h14. Thus, device B lost the arbitration and stopped communication. In I3C arbitration, the higher-address device will always lose and yield to the lower-address device.

I3C: A slew of new features

I3C brings a significant increase in the bandwidth of the serial bus, as well as a slew of new features. This article has touched on the higher-level features and functions of the bus but it’s not an exhaustive list of the features and commands possible. More details about the I3C specification are available from the MIPI Alliance.


This article was originally published on EDN.

Robert Perkel is an application engineer at 8-bit MCU business unit of Microchip Technology Inc.


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