GDDR6 DRAM Design Challenges on Signal Integrity

Article By : Nitin Juneja

Each component in the memory interface channel requires close attention to ensure that signal integrity is maintained.

Are you a system-on-chip (SoC) or system designer at one of the many OEM system companies with GDDR6 on your drawing board?

Design discussions are underway at a number of system companies about engaging in next-generation GDDR6 DRAM implementations. Unlike previous DDR generations, this one comes with a host of design challenges, requiring both SoC and system designers to carefully evaluate the complete GDDR6 memory interface in order to achieve successful designs.

Memory interface

The GDDR6 memory interface is best described as a high-speed, high-signal-count, parallel memory interface that uses single-ended signaling to communicate with DRAM memory in applications requiring high memory bandwidth and low latency. Included here are such applications as automotive ADAS, graphics/GPU, data center, and AI/machine learning.

As shown in Figure 1, this memory interface channel is the data path from the controller PHY to the DRAM receiver. It consists of the controller BGA package, the PCB, and the receiver package. Many design factors with respect to the channel significantly affect signal integrity. This article discusses some key design considerations.

Figure 1: Memory interface channel
(Source: Rambuse)

The controller BGA package relies on the flip-chip ball-grid array (FC-BGA) packaging for the benefits that it offers in greater pin density and improved power delivery parasitics. Greater pin density is achieved because the pins can be arranged in an area array with pin pitches as low as 0.4 mm.

With the large number of package pins available, it’s possible to parallelize the path of the power and ground to the circuits and reduce the inductance that these electrical paths would see through the package. The low-inductance paths significantly improve power delivery network (PDN) parasitics.

An FC-BGA package is a multi-layered laminate structure with a thick resin core, copper foils, and dielectric layers, as illustrated in Figure 2. The dielectric layers are also referred to as build-up layers in the package and are sandwiched between the copper foils. Signal traces and power planes are etched on the copper layers.

Figure 2: Cross section of a 4-2-4 package
(Source: Rambuse)

An FC-BGA package with two conductor layers in the core and four conductor layers in the build-up section is referred to as a 4-2-4 package. The flip-chip ASIC attaches to the BGA with either solder balls or copper pillars.

The GDDR6 memory sub-system moves data using single-ended signals at a high data rate of 16 to 20 gigabits per second (Gbps). Signal integrity at high data rates is affected by the material properties of the conductor and the dielectric. The dielectric materials in the FC-BGA and, subsequently, in the PCB absorb the magnetic energy from the signal transmission line and reduce the strength of the signal at the receiver.

Signal loss

The signal loss is measured in decibels and is known as insertion loss. It can be simply defined as the ratio of the strength of the signal at the receiver and the strength of the signal at the transmitter. When designing the GDDR6 FC-BGA, insertion loss needs to be minimized by reducing the channel length and/or by using low-loss dielectric materials.

In the controller package, smaller channel lengths can be achieved in a smaller package. In the PCB, smaller channel length can be achieved by placing the DRAM package as close as possible to the controller package. Given the constraints in most automotive and consumer PCB systems, it is usually possible to limit the PCB channel to between 30 mm and 60 mm.

Low-loss dielectric materials are available for packages and the PCB. In the case of the package, it is possible to use Ajinomoto build-up film (ABF) thin-film dielectric with a dielectric loss as low as 0.0044. For the PCB, it’s possible to use Megtron6 with a dielectric loss as low as 0.002. Using low-loss materials is an effective way to reduce the insertion loss for the channel.

Figure 3: Insertion loss improvement with channel length and with low-loss dielectric materials
(Source: Rambuse)

Figure 3 shows the benefit of using a low-loss dielectric material like Megtron6 over the standard FR-4 dielectric material. For a 60-mm channel routed on the PCB, using a low-loss material reduces the insertion loss by more than 50% while reducing the channel length from 60 mm to 44 mm. This has a 10% improvement on the insertion loss.

Skin effect

High-speed signals tend to travel at the surface of the conductor. This phenomenon is also known as the skin effect. In an FC-BGA package, the interface between the conductor and the dielectric is usually not very smooth and the surface roughness leads to increased signal insertion loss at higher data-rate transmissions.

Surface roughness is quantified with the metric Ra, which represents the arithmetic mean of the surface profile. Recent package substrate manufacturing innovations have made it possible to manufacture substrates with Ra as low as 250 nm.

As the signal travels from the transmitter to the receiver, any differences in the impedance along the signal path causes a signal reflection (return loss) and affects the quality of the signal eye diagram at the receiver. A typical signal path in a GDDR6 channel has many components, including C4 bumps, micro-vias, plated-through-hole vias, BGA balls, and signal traces in the controller package, DRAM package, and the PCB.

The impedance discontinuity due to the via, the C4 bump, and the BGA ball are difficult to control due the manufacturing process limitations, such as via drill size and BGA ball size. It’s usually possible to match the signal trace impedance to the receiver and driver impedance and minimize the return loss to improve insertion loss.

Plated-through-hole via design in the PCB can cause significant degradation to the signal insertion loss due to the presence of via stubs. Via stubs may need to be removed by back-drilling or by using blind or buried vias in the PCB.


The GDDR6 PHY is a data parallel interface in which many signals are sending and receiving data at the same time at high speeds. Some of these signals can couple to the adjacent signals in the package and interfere with the adjacent receiver signal. This phenomenon is known as crosstalk.

In the package substrate, this can happen when the signal traces are routed very close to each other on the same layer or when the signal vias through the core are placed very close to each other. Increasing the spacing between the “aggressor” signal and “victim” signal is the obvious solution.

However, this may not always be possible without adequately planning the layout of the signals, ASIC die bumps, BGA pins, and the vias in the substrate. To minimize the via crosstalk, BGA pins may need to be re-arranged so that there is a ground or a power pin (return path) between the multiple aggressor signals and the victim signal.

Fine-pitch BGA packages may have additional crosstalk due to vias being too close to each other. Trace routing on the package substrate needs to be planned to manage the routing density, and additional routing layers may be required.

In the PCB, through-hole vias under the BGA pins can add significant crosstalk. Rearranging BGA pins with adequate isolation and return paths helps to reduce crosstalk. Through-hole vias may need to be back-drilled to reduce the coupling of signals in the vias below the BGA package. Using blind and buried vias might also be an option to reduce crosstalk.


In this column, we’ve discussed several design considerations and methods associated with mitigating the challenges that GDDR6 DRAM implementation will pose. In particular, the importance of maintaining signal integrity spans throughout the interface channel. Special attention must be applied at each stage of the GDDR6 memory interface to successfully deal with signal integrity issues.

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