Generating track masks for SAMP processes

Article By : EDN Staff

Learn the decomposition requirements for generating track masks for SAMP processes while complying with all relevant DRC.

As any engineer who’s tried it can tell you, creating a design rule check (DRC)-compliant design for self-aligned multi-patterning (SAMP) processes is not a trivial matter. Decomposing the desired target shapes into appropriate mask shapes while complying with all relevant DRC requirements is a complex process.

Understanding the critical decomposition requirements and techniques for generating accurate track masks for the SAMP processes, as well as understanding the root cause of errors that occur during decomposition, are critical to the successful manufacturing of designs that rely on these processes.

The multi-patterning (MP) tools in electronic design automation (EDA) not only automate the decomposition process, but help engineers more quickly and accurately understand and debug situations where the drawn target shapes don’t enable proper track mask generation. IMEC and Siemens EDA (formerly Mentor Graphics), conducted a collaborative project to define and describe the automated decomposition process, using the Calibre Multi-Patterning tool as representative of EDA tool capabilities.

SADP/SAQP track decomposition

Self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) require a mandrel mask and cut/block masks for fabrication. The first step is to convert the target into mandrel and non-mandrel tracks. The separation between these tracks is defined by sidewall width. While SADP uses one sidewall generation step, SAQP requires two sidewall generation steps because separation between tracks in SAQP is defined by the second sidewall width. As these two processes use sidewalls, the spaces between metal lines—metal tracks—are constant in both.

As shown in Figure 1, all target shapes in the same track must be aligned with respect to each other and have the same width. Any gaps between target shapes must be filled with dummy metal; same is true for gaps between target shapes and the border of SADP area, the marker that defines the extent of the IP block. If a wide gap in the perpendicular direction is found, this gap must be filled with dummy tracks—tracks without any target shapes—to maintain constant spacing between the final generated tracks.

diagram of dummy tracksFigure 1 Dummy tracks are generated as needed to fill empty areas between target shapes, maintain constant spacing between tracks, and respect anchors. Source: Siemens EDA

As shown in the middle of Figure 1, the extra spacing between some of the tracks is not wide enough to generate three tracks while maintaining the required constant space between each track. To solve this issue, the Calibre Multi-Patterning tool generates two wide tracks instead.

How do you know which track should be assigned to the mandrel or non-mandrel group? That designation is actually somewhat arbitrary. If you have a particular preference, the Calibre Multi-Patterning tool lets you control the assignment through the use of anchor layers. For example, during the fabrication process, the generation of mandrel lines is different from the non-mandrel lines, so you may want to assign some nets based on connectivity or functionality to a specific mask. As shown in Figure 1, a target shape marked as a mandrel anchor is assigned to a mandrel track, and a target shape marked as a non-mandrel anchor is assigned to a non-mandrel track.

Due to various standard cell library design configurations, each metal layer may have a range of allowable track widths. The foundry defines these allowable track widths, either by defining a range containing allowable widths, or by assigning specific values to a set of allowable widths. The Calibre Multi-Patterning tool does not generate any tracks with widths outside these allowed ranges or set of predefined values, which helps you create masks that are compliant with the foundry’s constraints.

The set of track widths may also be limited to a specific sequence. The foundry defines any required track width sequence, which is usually defined as the sequence of track widths between two power rails. The Calibre Multi-Patterning tool can then match up this track width sequence specification with the target track polygons that are in the design and insert dummy tracks where needed, using the appropriate sequence of track widths (Figure 2).

diagram showing how to evaluate track width sequenceFigure 2 Dummy track insertion is based on a track width sequence as per foundry specification. Source: Siemens EDA

SALELE track decomposition

The SALELE process has two required track masks: LE1 and LE2. Because there is a separate mask for each track type, the SALELE process does not require continuous tracks or the use of dummy tracks to fill empty spaces. If the gap between target shapes on the same track is wide enough to be printed directly, then no dummy metal is needed to fill this gap.

If the gap between target shapes on the same track is smaller than the lithography limit (meaning it can’t be directly printed), then the Calibre Multi-Patterning tool fills the gap with dummy metal, and adds a cut/block shape to the block mask at this location to create the required isolation between target metal shapes, as shown in Figure 3.

diagram showing narrow gaps to be filled with dummy fillFigure 3 In SALELE decomposition, only narrow gaps between target shapes, which can’t be printed directly, must be filled with dummy fill. The generated shapes are then divided between the LE1 and LE2 masks. Source: Siemens EDA

After the filling process, the generated shapes are divided between the LE1 and LE2 masks. Anchoring in SALELE is similar to SADP, and equally important. Based on connectivity or functionality, you can assign any target shapes to a specific mask—LE1 or LE2—using the anchoring process.

[Continue reading on EDN US: IP block termination]

This project has received funding from the ECSEL Joint Undertaking (JU) under grant agreement No 783247. The JU receives support from the European Union’s Horizon 2020 research and innovation programme and Netherlands, Belgium, Germany, France, Austria, United Kingdom, Israel, Switzerland.


Jae Uk Lee

Jae Uk Lee is a senior R&D engineer in computational lithography (including SMO, OPC, and DFM) at IMEC. His research focus is EUV lithography and advanced patterning technology. He received his M.S. and Ph.D. degrees from Hanyang University. He may be reached at


Dr. Ryoung-han Kim

Dr. Ryoung-han Kim is the director of physical design/design automation, OPC/RET, and test-site/tapeout at IMEC. His scope at IMEC covers various R&D activities across logic and memory programs in photo-lithography, OPC, mask technology, PDK/design rule/design enablement, data preparation, and DTCO. He received his Ph.D. degree in electrical engineering from Texas A&M University and his B.S./M.S. from Yonsei University, Seoul, Korea.


David Abercrombie

David Abercrombie is the program manager for advanced physical verification methodology at Siemens EDA. For the last few years, he has been driving development of EDA tools that can solve the issues in design to process interactions that create ever-increasing yield problems. David received a BSEE from Clemson University, and an MSEE from North Carolina State University. He may be reached at


Rehab Kotb Ali

Rehab Kotb Ali is a senior product engineer at Siemens EDA, working on advanced physical verification technology. She currently specializes in RET, OPC and MP/SADP/SALELE processes and products. She received a B.Sc. in electronics and communications engineering from Cairo University, and a master’s degree in Nanotechnology from American University in Cairo. Rehab can be reached at


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