Hardware Design Requirement for LXI Device Powered over Ethernet

Article By : Chang Fei Yee

This article introduces the basic concept of LXI and PoE, and highlights the four key requirements for hardware realization to achieve LAN PHY compliance for device powered over Ethernet...

This article introduces the basic concept of LAN eXtensions for Instrumentation (LXI) and Power over Ethernet (PoE), and highlights the four key requirement for hardware realization to achieve local area network (LAN) physical layer (PHY) compliance for device powered over Ethernet. The LAN PHY compliance test is discussed in the later section of this article.

Introduction to LXI and PoE

LAN eXtensions for Instrumentation (LXI) is a standard for instrumentation controlled over Ethernet. Once the LXI device is hooked up to the local area network (LAN) infrastructure of any institution, the device can be controlled remotely from anywhere within the premise and even offsite through virtual private network (VPN). All LXI devices must be compliant with LXI Device Specification. In term of physical (PHY) connection, LXI device must be able to achieve data rate of 100Mbps during communication with its link partner, which is compliant with the specification of IEEE 802.3 Type 100BASE-TX.

On the other hand, Power over Ethernet (PoE) is the implementation of LAN switching infrastructure (i.e., power sourcing equipment or PSE) to supply power (i.e., 48Vdc) to the device linked to it, which means that PoE device (i.e., PD) is bus powered by PSE through LAN cable. The port pin assignment for PoE with 100Base-T is depicted in Figure 1. There are data signals and power lines over the LAN cable.

Fig. 1. Pin assignment for PoE with 100Base-T

Key Hardware Design Requirement

There are four key aspects of hardware realization that require designer's attention, which are discussed in subsection A, B, C and D respectively in this article.

A. Buck Converter Selection and Application

The first essential aspect is to select a buck converter compliant with IEEE 802.3at standard. This buck converter down converts the 48Vdc supplied by PSE to lower power nets needed by the sub-systems of the PD. The designer is required to configure the PoE buck converter based on the power loaded by the PD as categorized, where the list of class setting is depicted in Figure 2. For instance, buck converter has to be set as Class 1 for PD's power consumption between 0.44W and 3.84W. PoE buck converter off-the-shelf has an input port that facilitates designer to set the PoE class by hardwiring a discrete resistor.

Fig. 2. PoE class

B. TVS Protection

The second key consideration for LXI PoE device is transient voltage suppression (TVS) protection, where the TVS diode is placed as close as possible to the Ethernet connector (i.e., RJ45) of the device, depicted in Figure 3. Each data line of the Ethernet PHY transceiver IC is clamped between power net of the IC and reference ground using the TVS diode to safeguard the IC against the destruction caused by electro static discharge (ESD) and power surge. Overvoltage could happen to the line during hot-plug of the LAN cable with the RJ45 connector of the PD.

However, TVS diode with low parasitic capacitance (i.e., below 1.5pF) shall be selected for protection of the PD. A higher diode capacitance decreases the slew rate of signal transition, which would potentially fail the Ethernet connectivity between the PoE device and its link partner. Furthermore, the printed circuit board (PCB) trace that connects the data line and the TVS diode shall be kept as short as possible (i.e., less than 50 mil). A longer trace magnifies the negative impact of stub, which introduces additional capacitance to the data line and decreases the bandwidth of the transmission channel.

The stub effect is shown in Equation (1), where the quarter wave resonant frequency (i.e., bandwidth of the transmission line) is inversely proportional to the stub length. The aforementioned negative effect of parasitic capacitance (due to TVS diode) and trace stub length is proven in the simulated insertion loss (Sdd21) plots depicted in Figure 4. At 500MHz (5th harmonic of 100Mbps LAN), before inserting TVS diode, the Sdd21 due to 100 mil stub doubles versus 50 mil stub (i.e., -0.1dB for 50 mil stub versus -0.2dB for 100 mil stub). TVS diode of 10pF capacitance adds up 2.3dB insertion loss versus 1.5pF. TVS diodes off-the-shelf come with 0.85pF parasitic capacitance at least, some even as high as 50pF. Hence, TVS diode with low parasitic capacitance (i.e., below 1.5pF) shall be used.

Fig. 3. TVS diode on Ethernet PHY

fo = quarter wave resonant frequency (Hz)
c = speed of light (1.18×1010 inches/sec)
stublength in inches
Dk = dielectric constant

Fig. 4. Insertion loss plots for 1 inch Ethernet transmission channel with different stub length to TVS diode

C. Electrical Isolation

The electrical isolation of 1500V is another key consideration, as specified in IEC 60950-1:2001. RJ45 connector shall have clearance of minimum 4mm with other circuitry of the PD. Moreover, buck converter and RJ45 connector with 1500V isolation and Ethernet isolation transformer shall be used in PD. The simplified block diagram of the implementation is illustrated in Figure 5. The electrical isolation is necessary to safeguard the PD against damage by high voltages caused by cable discharge events (CDE).

Fig. 5. Isolation for PoE

D. Connector pins and integrated EMI Filter of RJ45

Hardware designers shall always use RJ45 connector with minimal pin stub effect on signal transmission. With reference to Figure 4, Sdd21 due to 100 mil stub doubles versus 50 mil stub. Hence, surface mount type of RJ45 shall be applied. Meanwhile, if through-hole RJ45 connector is used, not only the signal transmission lines shall be routed as close as possible to the PCB bottom layer (i.e., nearer to RJ45 pin tip), but also the excessive portion of the pin shall be trimmed, as short as possible, depicted in Figure 6.

Fig. 6. Through-hole RJ45 pins being trimmed

Besides that, the RJ45 connector with integrated EMI filter shall be applied in PD. The filter serves as common mode choke to suppress the EMI noise, which is crucial to minimize the radiated emission (RE) from the PD, in compliance with the EMI/EMC standard and regulation set by Federal Communications Commission (FCC) in the USA and other regulatory bodies around the world.
Figure 7 depicts the 3 meter RE test profiles for DUT with EMI filter versus without EMI filter in RJ45. At 100MHz (i.e., LAN frequency), DUT with EMI filter emits much lower radiation (i.e., 30dBuV) versus DUT without EMI filter (i.e., 40dBuV). At higher frequency range (e.g., 200MHz, 250MHz, 300MHz), RE level of DUT without EMI filter exceeds the specified maximum limit. Meanwhile, RE level of DUT with EMI filter passes the regulatory requirement.

Fig. 7. 3 meter RE test profile for DUT with EMI filter versus without EMI filter in RJ45

LAN 100Base-TX PHY Compliance Test

Upon hardware design completion, the prototype shall pass the LAN 100Base-TX PHY Compliance Test. The PD’s compliance with LAN 100Base-TX standard guarantees minimal bit error rate (BER) and robustness of the data communication between the PD and its link partner.

The test setup using oscilloscope DSO91304A installed with Ethernet compliance test software N5392A from Keysight is illustrated in Figure 8. The test setup and test flow using N5392A is simple. Once The PD (i.e., device under test) is configured to generate MLT-3 data pattern and the required compliance tests (i.e., peak voltage, overshoot, template, rise/fall time and DCD/jitter) are selected in N5392A, the tests are completed within 15 minutes. Figure 9 depicts the LAN PHY test report for DUT designed following the guideline mentioned above. It passes all the PHY test parameters.

Fig. 8. Test setup for 100Base-TX PHY compliance

Fig. 9. LAN PHY test report


All the hardware design considerations discussed in this article must be paid attention to in order to ensure the PD's compliance with the standards of electrical, safety and EMI/EMC.

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