Heterogeneous integration enables advanced IC packaging

Article By : Gareth Kenyon

Heterogenous integration technology enables semiconductor device manufacturers to combine components into a single composite device with complex and advanced functionality

Heterogeneous integration technology refers to the integration of separately manufactured components into a higher-level assembly, or system in package (SiP), that in the aggregate, provides enhanced functionality and improved operating characteristics.

Furthermore, components can be taken to mean any unit such as micro-electromechanical systems (MEMS), assembled packages for high bandwidth memory (HBM), for example, passive components, and others (Figure 1).

diagram of heterogeneous integration technology

Figure 1 A high-level view of how heterogeneous integration technology works. Source: Veeco Instruments

Not a continuation of Moore’s Law

Strictly speaking, Moore’s Law is an observation that calls for the density of transistors in an IC to double every two years. Integration density of transistors is becoming constrained at 2D, mainly due to the slowdown in gate length shrinkage, while 3D is being utilized to continue advancement. Stacked memory as a 3D chip is an example, where multiple layers of the same technology are stacked, increasing the integration density.

“More than Moore” refers to an increase in functionality density, integrating diverse technologies into a composite device. This may include stacking of chips and/or packages, using multiple semiconductor materials and a variety of electrical routing techniques such as ball grid arrays (BGAs), through silicon vias (TSVs), interposers, and wire-bonding. A more than Moore device might integrate logic, memory, sensors, and antennas from various front-end manufacturing nodes into a single package using heterogeneous integration.

Heterogeneous integration is nothing new

Heterogeneous integration is not a new concept. Multi-chip modules (MCM) have been around since the 1970s. However, advanced packaging techniques have revolutionized electronics package manufacturing. New packaging technologies have enabled integrating chiplets from different manufacturing process flows into a single package with a variety of functions. The diversity of these packaging technologies has increased greatly in the past two decades, driven by market demand for higher device performance at lower cost.

Power, performance, area, and cost (PPAC) have been the key drivers for the adoption of the heterogeneous integration technology. Lower power consumption, footprint reduction, lower latency, higher speed, and increased bandwidth are all major performance improvements that deliver advantages to the consumer.

Naturally enough, scaling is still a consideration in heterogeneous integration. Scaling of the interconnects, bump pitch, TSVs, and bond pads will help improve the PPAC of a device. This, in turn, creates important challenges for the advanced packaging industry regarding the process, tooling, and metrology improvements.

Paradigm shift in lithography

Photolithography has also been forced to adapt with the development of the advanced packaging industry. As the complexity of devices evolve, pressure on device and package scaling has become intense, giving rise to a plethora of research in established industry segments seeking to develop an opportunity. The resulting technological innovation requires new or enhanced collaborations between device, package, system designers, and manufacturers, disrupting the historical boundaries between the industry segments.

As heterogeneity increases, convergence of device, package, and PCB will increase, creating a multitude of advanced packaging solutions that have evolved to cater to specific systems. For example, high performance computing (HPC) applications demand 2.5D interposer technologies for fine pitch micro-bumping and redistribution layers (RDL). In contrast, consumer mobile and IoT markets require less stringent design rules that do not incorporate an expensive interposer, choosing to embed interconnect layers in associated mold compound using high density fan out (HD-FO) packaging technology.

Interposer (TSV) and fan-out (TSV-less) technologies are not mutually exclusive and can be combined in a single, mixed technology package. The end use case largely determines the package requirement, and therefore, defines the complexity of both the device and the package.

For lithography, there are two paradigms: the front end of line (FEOL) and back end of line (BEOL). Metallization interconnects have traditionally been considered a BEOL domain, but as 2.5D and 3D architectures emerge, this demarcation is blurred. The requirement for high performance interconnects necessitated vertical electrical connections—TSV or TMV—that pass right through the silicon or mold compound, complementing and supplanting traditional wire-bond and flip-chip solutions. Via technology has become essential for implementation of high-performance interconnects (Figure 2).

diagram of heterogeneous integration

Figure 2 Heterogeneous integration exhibits the TSV and interposer capabilities. Source: Veeco Instruments

RDL and bumping challenges

As interconnect technology changes, the lithography requirement to produce it also changes. Some prior BEOL processes now run using FEOL tools, and some BEOL tools are now performing at FEOL standards while running BEOL wafers. All photolithography processes emphasize feature resolution, critical dimension (CD) control, and overlay accuracy metrics while maintaining high productivity and low cost.

FEOL lithography tools that typically operate at high numerical aperture (NA) for resolution reasons are now tasked with fine line/space, via, and micro-bump patterning for initial interconnect definition. As the density of interconnect and redistribution layers increases, the challenges relating to thicker photoresist films, substrate warpage, and depth of focus become compounded and high NA lithography systems frequenting the FEOL are no longer capable of running these difficult processes.

Certain advanced packaging technologies employ more difficult process flows, leading to more difficult-to-manufacture wafers. Take, for instance, die shift and wafer topography on TSV-less reconstituted eWLB or fan-out type wafers, which create challenges for overlay and depth of focus, respectively, in advanced packaging photolithography process flows. This is where a different lithography approach is required, utilizing BEOL lithography tooling that has been developed to address these issues with practical yet versatile solutions. The BEOL is recognized as the domain for metallization and interconnects.

Next, flip-chip (C4) bumping is a well-defined and stable process that has been an industry standard for several years. Although it too has been subjected to scaling, bumping is still fundamental to advanced packaging for heterogeneous integration. Generally, bump lithography is performed with thicker photosensitive materials that benefit from tooling with a low NA and a high depth of focus to define the larger flip-chip bumps—C4 technology.

diagram of silicon wafer integrated fan-out technologyFigure 3 This is a conceptual implementation of multi-die with micro-bump, Cu pillar, and flip chip bumping, in this case without the need for TSV, using Amkor’s silicon wafer integrated fan-out technology (SWIFT).

However, as industry segmentation shrinks, drawing FEOL and BEOL closer together, BEOL tool flexibility has become critical. The capability to handle warped wafers, broadband exposure—GHI, GH & I-line wavelengths—for multiple film stacks, and variable NA for resolution adaptability with large depth of focus control have all proved paramount for high productivity, high yield, and good cost of ownership.

This flexibility will be extremely important, especially at outsourced semiconductor assembly and test (OSAT) facilities. Versatility to match a variety of FEOL exposure field sizes, substrate sizes, and material types are also an important consideration. The requirement of improved stage precision for tighter overlay, higher throughput for greater productivity, and tighter exposure uniformity for improved CD uniformity is merging FEOL and BEOL tool performance for leading-edge heterogenous integration technology applications.

Modern, leading-edge applications such as artificial intelligence (AI), HPC, 5G, IoT, and consumer mobile are driving demand for increased electronic device performance at ever lower costs. Heterogenous integration technology enables semiconductor device manufacturers to combine functional components from different manufacturing process flows into a single composite device with complex and advanced functionality.

Advanced packaging production demands created by these technologies challenge lithography and complementary processes to perform at a higher standard to support the required interconnect and TSV processing layer requirements. Here, device cost and lower productivity or yield due to increased complexity are the challenges that manufacturers will address. Initially, high-end applications will benefit from heterogenous integration before advancements in yield and process flow enable packaging devices to be cost-competitive for wider markets.

Gareth Kenyon is a senior product engineer while also carrying out technical marketing assignments at Veeco Instruments.

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