High-frequency resonant converter design considerations, Part 1

Article By : Sheng-Yang Yu

This power tip focuses on key parameters that affect switching component selection, as well as the effect of transformer intrawinding capacitance in a high-frequency resonant converter.

High-frequency resonant converter design considerations include component selections, design with parasitic parameters, synchronous rectifier design, and voltage gain design. This power tip focuses on key parameters that affect switching component selection, as well as the effect of transformer intrawinding capacitance in a high-frequency resonant converter.

The commercialization of wide bandgap (WBG) devices over the past decade has enabled the operation of power converters at much higher frequencies for higher power density. High-performance power supplies are just starting to include WBG devices – especially silicon carbide and gallium nitride field-effect transistors (FETs) – because of their output capacitance (Coss), gate charge (Qg), on-resistance (RDS(on)), and reverse-recovery charges (Qrr), all lower (or nonexistent) than silicon or silicon super-junction FETs at the same breakdown voltage level. A lower Qg reduces the driving power needed – Pdrive = VdriveQgFsw – and a lower RDS(on) reduces the conduction loss, where Vdrive is the driving voltage and Fsw is the FET switching frequency. Other than Qg and RDS(on), it’s also important to consider Coss and Qrr when selecting components in high-frequency converters.

In a resonant converter like the inductor-inductor-capacitor-series resonant converter (LLC-SRC) shown in Figure 1, the current in the resonant tank charges/discharges the Coss of the FETs (state 1 in Figure 2) in order to achieve zero voltage switching (ZVS). ZVS means that the FET drain-to-source voltage (VDS) reaches zero before its gate voltage goes high. Therefore, a lower Coss enables a shorter dead time under the same resonant tank current level to achieve ZVS. A shorter dead time means a larger duty cycle and a lower root-mean-square (RMS) current on the primary-side resonant tank and FETs, which means higher efficiency and the ability to operate the converter at a higher switching frequency.

Figure 1 LLC-SRC

To achieve ZVS, there is always a period during which the body diode of the FET conducts current – state 2 in Figure 2. If the FET has Qrr and is turned on again when the body diode still conducts current, the FET itself will create a reverse current to discharge Qrr and cause hard switching and high voltage stress – potentially damaging the FET.

Figure 2 Switching transitions of an LLC-SRC

Figure 3 illustrates this hard switching phenomenon during the startup process of an LLC-SRC as illustrated in Figure 1. When FET Q2 first conducts current, inductor current IPRI is built up. The current IPRI then conducts through FET Q1 channel and body diode. Without allowing the current to go in the reverse direction, FET Q2 turns on again. Because of the Qrr, FET Q1 self-generates a reverse current to discharge Qrr, which results in high voltage stress.

Figure 3 Hard switching due to Qrr

In a high-frequency resonant converter, the resonant tank impedance is generally much lower than that in a low-frequency resonant converter. Therefore, the startup inrush current in a high-frequency resonant converter is expected to be higher. Using the LLC-SRC in Figure 1 as an example, when the output voltage is zero (the initial condition at startup), the only impedance limiting the startup current when Q2 first conducts is Lr – the series resonant inductor in the LLC-SRC. High-efficiency and high-frequency resonant converter designs, especially bus converters, generally minimize Lr in order to improve efficiency. A smaller Lr value makes the startup current higher under the same startup frequency and thus more vulnerable to Qrr-related hard switching. Therefore, it is essential to use low Qrr FETs in high-frequency resonant converters.

Harnessing the aforementioned benefits of WBG devices, it is possible to operate isolated resonant converters in the megahertz range, which is 5 to 10 times faster than traditional isolated power supplies. In this “higher frequency” domain, many parameters once considered “negligible” during the converter design process are no longer negligible, such as the transformer intrawinding capacitor.

In the traditional resonant converter design process, the designer must ensure that the energy stored in the resonant tank is higher than the energy stored in the FET Coss so that Coss depletes the energy stored in the resonant tank to achieve ZVS. Taking the LLC-SRC shown in Figure 1 as an example, Equation 1 ensures the validity of this inequality:

where ILm is the peak current of the magnetizing inductor Lm and Vin is the input voltage of the LLC-SRC. Equation 1 can be rewritten as Equation 2 by applying Ohm’s law for the inductor to Lm:

where n = Np:Ns1 (assuming Ns1 = Ns2) is the transformer turns ratio and Vout is the output voltage.

When resonant converter designs need to cover a wide operation range and holdup time, Lm is generally much smaller than the value on the right side of Equation 2 in order to keep Ln = Lm/Lr low (applying Ln values from 4 to 10 in a closed-loop LLC-SRC design). When resonant converter designs such as bus converters require high converter efficiency, maximizing Lm lowers the primary RMS current for a lower conduction loss. In this case, the Lm value will be closed to the value on the right side of Equation 2. Equation 2 only represents the ideal condition with an ideal transformer, however. In a real transformer, many parameters could affect the Coss charge and discharge capability. The most critical parameter is the intrawinding capacitance.

Figure 4 shows a simplified circuit model during a switching transient in an LLC-SRC, where current on Lm (ILm) discharges Ceq (the Coss of two FETs in series with resonant capacitor Cr), assuming Cr as a voltage source. Without the transformer intrawinding capacitance (CTX), all of ILm goes to Ceq and Equation 2 is valid. But with the presence of CTX, some of ILm has to go to CTX to change the transformer winding polarity, which reduces the Coss discharge capability and creates the possibility of losing ZVS. Therefore, it is essential to keep CTX lower by keeping layers of primary winding apart from each layer with distance as well as layers distance of secondary windings.

Figure 4 The effect of a transformer intrawinding capacitor

A rule of thumb in determining the Lm value is to use just half of the maximum Lm value calculated using Equation 2, as it is generally difficult to predict the CTX value before actually building a transformer. CTX generally falls inside the range of 22 pF to 100 pF in a converter with a 400-V input. It is also very useful to model CTX in a circuit simulation once the transformer structure is fixed, in order to ensure a low-enough Lm with margin.

In the next installment of this series, I will focus on synchronous rectifier design challenges in high-frequency resonant converter designs.

Sheng-Yang Yu is an applications engineer at Texas Instruments.

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