Never in recent memory at DesignCon has talk of a speed doubling changed so much in just one year. PAM4 is now firmly established as the modulation for 112G.
At DesignCon 2018, 112 Gbps was all over the conference and exhibit hall. Even just a year ago, engineers were still talking more about 56 Gbps speeds than 112. This year, all agree that 56 Gbps speeds have been achieved. It’s time to move on.
Throughout the conference sessions, panels, and exhibits, 112G was everywhere. Test-equipment companies and interconnect companies were demonstrating 112G systems, all using the same ICs from Credo and running four-level pulse-amplitude modulation (PAM4). The general agreement is that non-return-to zero (NRZ, also called PAM2) has finally reached its limit, as least for longer reaches.
Now that it’s time to move past 56 Gbps speeds, a panel session called “CEI-112G: Every. Last. Thing. Matters.” (Figure 1) looked a what’s needed to make a 112 Gbps common electrical interface (CEI) for optical transmission systems.
CEI standards are administered by the Optical Internetworking Forum (OIF). OIF-CEI 4.0, which included clauses for CEI-56G interfaces was approved on December 29, 2017. With that done, OIF is looking toward CEI-112G (Figure 2).
While there are five definitions for reaches in 56G, Nathan Tracy of TE Connectivity noted that 112G could have more or fewer definitions. That depends on how the technology develops. Currently, OIF has three such projects underway:
The chip perspective
“Multichip modules are the new PCBs,” said Brian Holden of Kandou Bus. “ICs have achieved such a complexity that yields can’t keep up. So, it’s better to use smaller chips and have electrical data connections between them.” The CEI-112G in MCM project was launched in January 2017 with the goal of defining a 112 Gbps interface at reaches up to 1 cm through no connectors. The standard will support data transmission from CMOS ICs to devices made from processes such as SiGe and GaN. The 112 Gbps XSR links won’t use forward-error correction (FEC) because that process slows down the throughput. Therefore, these links need low bit-error ratio (BER) performance of 1E-12 or lower, preferable 1E-15.
Holden acknowledged that traditional NRZ is out of the question at 112 Gbps, but neither did he advocate for PAM4. Instead, Kandou Bus favors CNRZ-5 encoding, which transmits five bits over six wires (“C” stands for chord signaling, see Figure 3).
With CNRZ-5, each of the five signals has a single binary-shaped eye at the decision point, as opposed to PAM4's three eyes. Holden showed a set of CNRZ-5 eyes at 69.6 Gbaud (Figure 5). "When you start chopping up chips, you need a lot of bandwidth and minimal power consumption." Holden claims that CNRZ-5 provides better signal integrity than PAM4. But, CNRZ-5 needs six wires as opposed to PAM4's two wires. That might not be an issue for MCM communications.
For chip-to-module communications—Very Short Reach —Semtech’s Ed Frlan noted that SFP-DD modules will support CEI-112G-VSR and will use PAM4 with forward error correction (FEC). VSR is unique compared to other reaches because it’s the one that connects to optical modules that will re-time the signals before sending them to the fiber (Figure 5). In addition to FEC, these modules will add decision-feedback equalization (DFE), feed-forward equalization (FFE), and continuous time linear equalization (CTLE). FEC lets the raw BER increase to 1E-6. After FEC, BER reduces to 1E-15.
Because 112 Gbps PAM4 needs the same bandwidth as 56 Gbps NRZ, the next generation of pluggable optical modules can use the same form factor for similar electrical distances as 56G-NRZ. Optical module manufacturers will still have the option of implementing analog or digital signal processing at 112 Gbps speeds.
Frlan then explained why PAM4 wins over NRZ and PAM8: signal loss versus eye size. PAM4 is the modulation of choice, but it isn’t without technical challenges. For example, PAM4 requires a combination of equalization and FEC. The tradeoff is BER versus cost and power. The energy-per-bit for 112G is yet to be determined, though increased from 2.8 pJ/bit at 28G to 3.0 pJ/bit at 56G. Another undetermined issue is that of channel impedance, which had been 100 Ω but could drop to 92 Ω or 85 Ω. That will make PCB design even harder. Further, MCM packaging will have to improve at 112 Gbps, even with PAM4 because of the smaller eye openings. Frlan noted that implementations (analog or digital) for these signals still need work.
[Continue reading on EDN US: PCB and measurement issues]
—Martin Rowe covers test and measurement for EDN and EE Times. Contact him at martin.rowe@AspenCore.com