How 3D NAND flash works, what lies ahead in its density roadmap

Article By : Maarten Rosmeulen and Jan Van Houdt, imec

Here is how and why NAND flash transitioned from 2D to 3D storage densities and what challenges lie ahead with addition of more layers.

For several decades, NAND flash has been the primary technology for low-cost and large-density data storage applications. This non-volatile memory is present in all major electronic end-use markets, including smartphones, servers, PCs, tablets and USB drives. In the conventional computer memory hierarchy, NAND flash is located the furthest away from the central processing unit (CPU), and is known to be relatively cheap, slow, and dense compared to static random-access memory (SRAM) and dynamic random-access memory (DRAM).

The significance of the flash memory segment is reflected by its impressive share in the global semiconductor capital expenditure (capex), where it accounts for about one third. Its success is related to its ability to continuously scale storage density and cost, the main drivers for NAND flash technology development. About every two years, the NAND flash industry has been able to substantially improve bit storage density, expressed in terms of increasing Gbit/mm2.

Along the road, several technology innovations have been introduced to maintain this trendline. Until recently, NAND flash memory cells were arranged in a planar configuration, using floating gate transistors for their memory operation. A floating gate transistor consists of two gates: a floating gate and a control gate. The floating gate is isolated from the rest of the transistor structure and is usually made of polysilicon. The control gate is an ‘ordinary’ transistor gate.

Figure 1 The floating gate is isolated from the rest of the transistor structure. Source: imec

Writing of the memory cell is accomplished by applying a pulse to the control gate, which forces electrons in (or out) of the floating gate, based on a tunneling mechanism. The presence (or absence) of charges alters the transistor’s threshold voltage, a shift that is referred to as the memory window. Information is thus encoded in the threshold voltage of the floating gate transistor, and reading is done by measuring the drain current. The charges stored in the isolated gate remain unchanged for long periods of time, giving the memory its non-volatile character.

Floating gate has been the common approach for 2D NAND for over 20 years, offering reliable operation despite its rather complex structure. Here, bit storage density improvement has been enabled by reducing the dimensions of the floating gate cell. However, 2D-NAND scaling is saturated at about 15 nm half pitch, mainly because of array reliability and electrostatic interference issues.

Going 3D to lower cost per bit

A further increase in bit storage density was brought about by transitioning to the third dimension, not by stacking 2D NAND-like layers, since the number of process steps required to do so would dramatically add to the cost. The basic idea behind ’true’ 3D NAND is to stack cells to form a vertical string, thus reaching a higher density per unit area. In this configuration, cells are still addressed by horizontal word lines.

The most common fabrication approach, the gate-all-around (GAA) vertical channel method, starts with growing an oxide/sacrificial-nitride (word-line) layer stack. Next, cylindrical holes are formed by drilling down through the stack using advanced dry etch tools. Tunneling and trapping layers are deposited along the sidewalls of the hole. To complete this ‘punch and plug’ process, a thin polysilicon channel is deposited within the hole, followed by a core filler to form a macaroni-like construct.

In the next step, nitride is removed and replaced by the word-line metal. In these GAA structures, the cylindrical gates wrap around the channel structure, which enhances carrier injection into the trapping layers, as such enlarging the program/erase window.

Figure 2 In a representation of a typical 3D NAND flash structure, BL = bit line, WP = word plate, BSP = bottom select plate, SP = source plate and TSL = top select line. Source: imec

By adding more layers instead of shrinking feature sizes, the NAND flash industry abandoned the classical way of scaling. First commercial 3D NAND products were introduced in 2013 with stacks counting 24 word-line layers (128 Gb). Depending on the supplier, variations in the structure exist, known by different names such as V-NAND and BICS.

As such, 3D NAND has been the first and (so far) sole technology to bring true 3D products to market. In the years to follow, many more layers have been put on top of each other to maintain the bit density scaling trendline. Recently, some of the major players introduced 176-layer 3D NAND-based products, and this trend of increasing layers is expected to continue in the years to come.

From floating gate to charge trap

Along the road, additional innovations have been implemented to either facilitate the challenging 3D process or to allow a further increase of the bit density. An example of the latter is an increase of the number of up to 4 bits per cell, which is a true asset of NAND flash technology. With 4 bits, for example, the multi-level cells use 16 discrete charge levels in each individual transistor, enabled by the sufficiently large memory window.

Another notable innovation was the replacement of the floating gate cell by a charge trap cell, which involves a more simplified process flow. The working principle of both cell types are relatively similar, but in a charge trapping cell, the trapping layer is an insulator—usually silicon nitride—which provides less electrostatic interference between neighboring cells. This charge trap cell is now the base of most 3D-NAND structures.

Toward increasing bit storage densities

To maintain the NAND-flash roadmap, some major players recently announced an increase of the number of layers to 500 or more. Following the trendline, this number will increase to 1,000 before the end of the decade. Increasing the number of layers introduces ever higher processing complexities; it challenges deposition and etch processes and causes stress to build up inside the layers. To address some of these challenges, NAND flash makers recently began splitting up the number of layers into two or more tiers and stacking the individually processed tiers on top of each other.

There is, however, a growing concern that without major innovations this evolution will gradually reduce the cost efficiency of the NAND flash storage products. The increase in layer count requires an investment in highly advanced deposition and etch tools. And the trend of stacking multiple tiers will dramatically add to the mask count and number of processing steps and time. It could also cause the storage roadmap to slow down with stacks of 1,000 layers being unavailable until 2030.

As layer count increases, there is pressure to shrink the layer thickness and control the height of the stack for patterning and stress reasons. This z-pitch scaling involves a reduction of the height of all materials that are involved in the stack, including word-line metals and oxides, which bring along specific challenges.

Z-pitch scaling

Z-pitch scaling is likely to be complemented by a further reduction in x-y dimensions as well. This would require major innovations in the memory unit cell, which has remained unchanged during the years of 3D NAND development. Therefore, new materials and cell architectures are being explored as alternatives for today’s GAA NAND flash cell.

One notable development is a trench-like architecture to connect the transistors. In this architecture, the memory cells are no longer circular. They are implemented at the sidewall of a trench with two transistors at opposite ends of the trench, which significantly increases bit density. From an operational point of view, this trench cell resembles a planar unit cell (being put upright) compared to the circular GAA NAND flash cell.

Although it comes with a slight penalty in electrical characteristics—such as the program/erase window—the unit cell area in a trench-like configuration can be reduced in the x-y direction compared to a ‘GAA’ cell. As such, the trench cell is put forward as a next generation NAND flash cell architecture, expected to reduce the x-y pitch from today’s 140 nm (effective) to about 30 nm.

Figure 3 Here is a comparison of gate-all-around architecture (top) vs. trench NAND flash cell architecture (bottom). Source: imec

In a more distant future, we expect that more disruptive ‘post-NAND’ innovations—such as imec’s liquid-based concepts—will be needed to continue the density scaling trendline and enter the terabit/mm2 era.

Editor’s Note: This is the first part of the two-article series on the current state of the NAND flash technology and what lies ahead in its density scaling roadmap. The following article will take a sneak peek at the advancements in the NAND flash technology realm.

This article was originally published on EDN.

Maarten Rosmeulen is program director of the Storage Memory program at imec.

Jan Van Houdt is a program director at imec.


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