How NOR flash helps overcome design challenges in wearables

Article By : Linus Wong and Wilson Yen

Memory is a key design factor in enabling innovative new features and functionalities in ultra-compact wearable and hearable devices.

Although wearable and hearable technologies seem like an extension of the previous generation of handheld devices, the innovative features needed to improve their value, user experience, and functionalities add a significant level of complexity. For example, adding sleek features and functionalities into a smartwatch has to be done within a rigid form factor and power constraint.

So, as we look at even smaller devices, such as hearing aids and earbuds, there are tougher restrictions that need to be met, specifically product weight. To enable easy-to-implement revisions and continuous improvements to these products functionalities in next-generation devices, wearables and hearables rely on memory. Memory is a key design factor in enabling these advanced devices.

Features required to deliver a superior user experience

Adding innovative features to a system can substantially increase code size. For example, vital sign monitoring requires significantly more data memory to implement additional design aspects such as security, over-the-air (OTA) updates, datalogging, and artificial intelligence (AI).

Next, security continues to become increasingly critical for every connected device and requires ongoing updates. For wireless devices like smartwatches, these updates are more often implemented using OTA mechanisms, which require sufficient memory to maintain and authenticate a second code image before transferring control to the new code.

Many devices are beginning to implement data logging as well. The impact of logging the user experience, data is just starting to be explored and will enable a whole new range of customization capabilities. Devices that currently track users, such as health monitors, will employ more sensors and, consequently, capture more data.

For the next generation of those devices, AI at the edge will become a disruptive trend, leading to an increase in memory size requirements. These edge devices use advanced AI systems to run machine learning (ML) algorithms to process data locally on the device for functionalities such as speech recognition, face-ID, fingerprint detection, and health monitoring. Due to lower cost, small size, and power efficiency, these devices rely on microcontrollers (MCUs) to run complex ML algorithms. MCUs deploy dedicated cores for parallelized processing, enabling ML models to be run and optimized on the device itself.

Memory’s role in product differentiation

All of these new capabilities drive the need for more non-volatile memory, meaning memory that has the capability to retain stored data even when powered off. Since many wearables and hearables are battery-operated, NOR flash is often the memory of choice given its fast read access, endurance, and reliability.

In fact, the market for NOR flash for smartwatches, wireless earbuds, and other body-worn devices is expected to grow from $90 million in 2019 to more than $265 million by 2024 (Source: Gartner, ABI, and internal Infineon estimates). This growth is fueled by the increase in demand for memory in connected devices in segments such as automotive, medical and industrial. At the same time, increasing density requirements are anticipated as well, moving from lower density 64 Mb memories to mid-density 256 Mb for wearable devices.

Physical size is arguably the most crucial aspect of these memories as die size directly determines the cost, final device footprint, and ultimately the form factor of the end product. One of the unique requirements of hearables and wearables is that the height or profile of a memory device matters. Thus, the depth of the memory die must also be optimized, and in some applications, like hearable devices, weight is also critical.

For these reasons, memory manufacturers continue to develop innovative technologies and new architectures that improve die size and power consumption. Take the example of SEMPER NOR flash family, which utilizes proprietary MIRRORBIT technology to store two data bits per cell, doubling the density in the memory portion of the device. The difference is substantial as it makes possible higher-density memory in a smaller footprint. A typical 256 Mb NOR flash has a die size on the order of 18 mm2. Using MIRRORBIT technology, 256 Mb can fit on a 13.6 mm2 die.

The memory also needs to be available to manufacturers as a die. Note that a standard approach for wearables is to use tailored packaging such as a wafer level chip scale package (WLCSP) with ball grid array (BGA) connections. In short, manufacturers use their package to integrate multiple processors—such as CPU and DSP—with the memory die of their choice in a single package, known as system-in-package (SiP), as shown in Figure 1. This, in turn, leads to the need for higher-density memory devices since they now need to store the application code and data of two processors. To enable these SiP devices, SEMPER Nano is offered in known good wafer (KGW) format, which OEMs can integrate with their processor(s) of choice.

Figure 1 Traditional hearables and wearables need external NOR flash to store code, data, and data logs (left). Applications with an extremely tight footprint, such as wireless earbuds with true wireless stereo (TWS) capabilities, utilize a high-density stacked-die architecture that combines an MCU plus DSP with memory in a single chip-scale package (right). Source: Infineon

Optimization for lower losses

Traditionally, memory devices are commodities designed to serve a wide range of applications. However, the tight constraints of the hearables and wearables markets require the use of memory explicitly optimized for size, power, and reliability.

There are several ways NOR flash can be optimized to minimize power consumption. Traditionally, low power is achieved by lowering standby current and active read current. Deep power down mode can significantly extend battery operating life to improve power efficiency further. To put this in perspective, SEMPER Nano NOR flash has a typical standby current of 5.0 A, which is 54% lower than SEMPER NOR flash, and the typical deep power-down mode drops to 1 µA, 23% lower than SEMPER NOR flash (Figure 2).

Figure 2 SEMPER Nano NOR flash power consumption is compared to SEMPER NOR flash. Source: Infineon

The key to lower power consumption is minimizing the time it takes the memory to transition from active to standby mode. To maximize power savings, the memory needs to be able to drop into standby mode immediately to avoid needlessly wasting power (Figure 3).

Figure 3 SEMPER Nano NOR flash integrates a processor to offload power and reliability processing from the application CPU. Source: Infineon

Fast read access is essential for features like “instant on.” No one wants to wait for their earbuds to boot up. Here, NOR flash memories are built on an internal parallel array interface to allow speedy read times, making it possible to boot up larger programs faster.

The fast access and low power of NOR falsh make it possible to run code directly from flash, which is known as Execute-in-Place (XiP), further reducing the time for a device to turn on. This unified memory approach combines code, data, and logs in a single memory chip. It significantly reduces the overall physical memory footprint by eliminating RAM for code and data storage. It also enhances overall reliability, lowers power consumption, and enables smaller form factors and a simplified design.

Better memory equals better wearables

The key to success and profitability in the wearables and hearables markets is differentiating products with innovative features like advanced fitness and medical monitoring to deliver a superior user experience. These features increase the need for higher density NOR flash memory optimized for size, low power, and reliability. The integrated reliability capabilities of NOR flash—with the ability to store code, data, and logs in a single unified memory—simplifies and accelerates designs while enabling developers to meet the tight design constraints of these applications.

This article was originally published on EDN.

Linus Wong is director, product management at Infineon Technologies.

Wilson Yen is senior application manager at Infineon Technologies.


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