How to create a bidirectional I2C to SPI bridge
Article By : Oleksandr Lek
Many devices interact via the I2C and SPI data protocols. This article shows how to convert between these two protocols using the GreenPAK SLG46811 IC.
Many devices interact via the I2C and SPI data protocols. In this article, we’ll show how to convert between these two protocols using the GreenPAK SLG46811 integrated circuit (IC).
Because of its small size and high functionality, as well as its low cost and current, this is an excellent choice for this application.
How Does the Conversion Work?
The SLG46811V can convert in both directions, from I2C to SPI and vice versa.
Figure 1: Application Circuit
Figure 1 shows a typical converter schematic. The I2C bus is connected to PIN5 and PIN6, and the SPI bus is connected to PIN9, PIN10, PIN11, and PIN12. PIN8 is used to control the transmission direction. The I2C bus must be pulled up to VDD.
The conversion direction is selected by the nSPI/I2C signal. This circuit provides the transmission of four bytes, one of which is the I2C control byte.
Figure 2: Design Implementation
This design was created using free GUI-based GreenPAK Designer software (a part of the Go Configure™ Software Hub). The complete design file is available here.
SPI Data Reception and I2C Data Transmission
When the nSPI/I2C signal is low, the IC receives SPI commands and transmits I2C commands.
Figure 3: SPI Data Reception
The SPI_EN signal determines the start and stop of SPI data reception. When the signal SPI_EN changes from high to low, the IC reads from the input SPI_DATA_IN. In synch with the clock signal SPI_CLK, the IC reads the data in the shift registers SHR 0 – SHR 3.
Figure 4: I2C Data Transmission
When the data is fully received, the signal SPI_EN goes high and the IC begins forming I2C packets. EDGE DET detects when the data is received, which translates the output of the SRFF trigger to 1. This allows the operation of the extended pattern generator (EPG) and the clock generator. The EPG unit deals with the formation of the I2C packets and controls the data issuance process.
Figure 5: EPG Waveform
The EPG unit records a set of patterns for generating I2C operation signals. Output OUT0 is used to form the Start, Stop and ASK bits. Output OUT1 generates a clock signal for I2C_CLK. The OUT2 signal provides a data offset in the SHR registers. Upon completion of I2C transmission, the OUT3 signal converts the SRFF trigger to 0, after which the system enters the initial state.
For example, we will try to change the counter data CNT0 in the SLG46826 using the SPI/I2C bridge.
Figure 6: Test Schematic
Figure 6 shows a test connection diagram of the SPI/I2C bridge built on the SLG46811 and the generator built on the SLG46826. The SLG46826 has PIN8 and PIN9 for the I2C bus connection and PIN17 for the pulse output.
Figure 7: SLG46826 Internal Schematic
The following is a key for Figure 8:
SLG46811
Channel 1 (yellow/top line) – PIN5 (I2C_CLK) with external 5kΩ pull up resistor
Channel 2 (light blue/2nd line) – PIN6 (I2C_DATA) with external 5kΩ pull up resistor
B1 – I2C data decoding
B2 – SPI data decoding
D0 – PIN12 (SPI_EN)
D1 – PIN11 (SPI_CLK)
D2 – PIN10 (SPI_DATA_IN)
SLG46826
D5 – PIN17 (PULSE_OUT)
Figure 8: SPI Data Reception
Figure 9: I2C Data Transmission
I2C Data Reception/SPI Data Transmission
When the nSPI/I2C signal is high, the IC operates in I2C slave / SPI master mode.
Figure 10: I2C Data Reception/SPI Data Transmission
In this mode, I2C data reception and SPI data transmission occur simultaneously. The following components are used to detect the I2C start / stop combination: P DLY in the EDGE mode of the detector, 3-bit LUT8, 3-L11, and DFF4. When the start combination arrives, the output of the trigger DFF4 goes to 0, which allows the EPG to operate and also activates the SPI_EN signal. The second part of the EPG generates signals for processing data coming from the I2C and also generates an ASK response signal. Data from I2C is transmitted immediately to the output SPI_DATA_OUT. SPI_CLK is clocked with I2C_CLK only for the time of service combinations such as Start, Stop, and ASK, when SPI_CLK clocking is suspended. When the Stop combination arrives, the output of the trigger DFF4 goes to 1, which puts the EPG in the initial state and signals the SPI bus signal SPI_EN to complete the data transmission. Some IC outputs have an output-enable (OE) signal to change the direction of operation.
Figure 11: EPG Waveform
For receiving I2C commands and transmitting SPI commands, we use EPG signals:
OUT5 – blocks the operation of the detector Start / Stop and inverts the CLK signal of the EPG unit when forming the ASK signal.
OUT6 – generates an ASK signal.
OUT7 – controls the SPI clock.
The following is a legend for Figure 12:
Channel 1 (yellow/top line) – PIN5 (I2C_CLK) with external 5kΩ pull up resistor
Channel 2 (light blue/2nd line) – PIN6 (I2C_DATA) with external 5kΩ pull up resistor
B1 – I2C data decoding
B2 – SPI data decoding
D0 – PIN12 (SPI_EN)
D1 – PIN11 (SPI_CLK)
D2 – PIN10 (SPI_DATA_OUT)
Figure 12: Testing Result
Conclusion
In this article, we implemented an I2C/SPI converter using the GreenPAK SLG46811 IC. GreenPAK ICs offer many functional elements to implement a variety of circuit designs. There are more than 50 ICs in the GreenPAK product family, and each has its own special features and functions. They allow for a significant reduction in the number of external circuit elements, and the ability to develop systems with highly specific requirements. Additionally, GreenPAK products enable very rapid design time and provide low power consumption, a small board area, and low cost.
This article was originally published on EEWeb.
Oleksandr Lek is an applications engineer at Renesas Electronics.
