How to implement a PWM fan driver using configurable chips
Article By : Gabriele Mantovani
Here is how to configure a power management IC to implement a PWM fan driver with temperature proportional speed control and lock detection for a 12V 2-wire fan.
Cooling fans are widely used and are extremely important in electronic devices, especially for those constantly running. That includes power supplies, servers, computers, and telecommunication equipment.
Low-cost cooling systems are often based on 2-wire fans that constantly run at full speed. The absence of temperature proportional speed control and the inability to detect fan lock—usually possible only with more expensive 3-wire fans—shortens the fan life and can lead to fatal damage for the system being cooled.
This article describes configuring a power management IC—SLG47105—to implement a smart pulse-width modulation (PWM) fan driver with temperature proportional speed control and lock detection for a 12-V 2-wire fan. It represents a low-cost solution with minimal external components.
Figure 1 A brushless DC fan has been used in this application. Source: Renesas
Cooling fans commonly use brushless DC motors with a simple internal commutation circuit based on a Hall sensor, powered with a DC voltage. The speed of the fan is proportional to the DC voltage and can be controlled with PWM technique.
Here is a brief outline of how engineers can implement a PWM fan driver in their products, starting with the basic construction and operating principle of this design approach.
Construction and operating principle
This design has 4 inputs and 1 output:
PIN # 2 is for analog input to control the fan speed
PIN # 3 is for control mode selection input
PIN # 14 serves PWM input for direct control of the output driver
PIN # 17 serves shutdown input to disable the fan
PIN # 16 is for fault output, active low
Figure 2 Here is what a typical application circuit looks like. Source: Renesas
In the application circuit shown above, the input mode is connected to GND and the design works in the “analog mode” as the fan speed is proportional to the voltage on PIN # 2. The design also allows engineers to control the output driver directly with a PWM signal on PIN # 14. In this case, the input mode must be connected to VDD (“digital mode”).
PIN # 19 and PIN # 20 are used to detect temperature thresholds. They must both be connected to PIN # 2 in “analog mode” and VDD in “digital mode”.
The above table shows fan parameters.
Figure 3 The prototype shows a low-cost solution with minimal external components. Source: Renesas
Anatomy of HVPAK design
This circuit design has been created in the GreenPAK Designer Software, a part of the Go Configure Software Hub, which is available for free and lets engineers create circuit designs without knowledge of any programming language. The full design file is available under this link.
Figure 4 The diagram highlights HVPAK design building blocks. Source: Renesas
Voltage-proportional fan speed control
The fan speed control block allows engineers to control the fan speed using a voltage input. The duty cycle of the PWM that drives the fan is proportional to the input voltage (between 0 V and 3 V).
Figure 5 The duty cycle of the PWM that drives the fan is proportional to the input voltage. Source: Renesas
The differential amplifier with integrator and comparator macrocell amplifies the voltage on the high-voltage outputs, extracts the mean value, and compares it with the reference voltage (voltage VIN on PIN # 2). The macrocell activates the “equal” or the “upword” outputs according to the result of the comparison.
The PWM macrocell uses the “equal” and “upword” signals to increment or decrement the duty-cycle counter, which stores an 8-bit value, representing the duty cycle of the generated PWM waveform. In this way, the block implements a loop that adjusts the duty cycle to facilitate the following expression:
Vmean = 4*VIN
Here, Vmean is the mean voltage on the fan, and the constant 4 is the gain of the differential amplifier.
So, the output duty cycle depends on the input voltage according to the following equation:
dc (%) = (4VIN / VDD2_A)100
In this example, where VDD2_A is 12 V, we get a duty cycle of 100% with VIN = 3 V. Figure 6 shows the output PWM waveform (CH1) and input voltage (CH2) where VIN ≈ 1.5 V and thus dc ≈ 50%.
Figure 6 The output duty cycle depends on the input voltage. Source: Renesas
Lock detection and auto-restart
This block can detect if the fan stops, either because it is forced to stop or because it is disconnected from the driver. When a lock is detected, the output driver is disabled. In the first case, it’s also necessary to protect the fan from fatal damage. In both cases, the block is useful to activate a fault output so that the system can protect itself from overheating.
In addition, when a lock is detected, this block attempts to automatically restart the fan after a programmable delay time.
Figure 7 The lock detection and auto-restart block is based on current measurement accomplished with a resistor connected in series with the driver. Source: Renesas
As shown in the above figure, the block is based on current measurement acquired by means of a resistor connected in series with the driver. The resistor provides a voltage signal proportional to the motor current at the sensor input. To understand how to detect fan lock, we need to understand the circuitry of a DC brushless fan.
Figure 8 Brushless DC fans use a simple switching circuit. Source: Renesas
Brushless DC fans use a simple switching circuit like the one shown in Figure 8. The Hall sensor switches on one of the two transistors according to the rotor position to activate the correct coil and ensure rotation. These commutations cause short and periodic interruptions of the fan current, as shown in Figure 9. On the other hand, if the fan is locked, there is no commutation and no current interruption, as shown in Figure 10.
Figure 9 In a fan current waveform during normal operation, the signal on the sensor pin is amplified by a factor of 120 for measurement purposes. Source: Renesas
Figure 10 There is no commutation and current interruption if the fan is locked. Source: Renesas
The comparator CCMP0 is used to provide a pulse every time there is a current interruption. The falling edges of these pulses keep triggering the CNT1/DLY1 macrocell (configured in delay mode), which will hold its output low as long as the pulses keep coming. If no pulses occur for about 50 ms, the output will go high, triggering the CNT3/DLY3 (configured in one shot mode) to provide a negative pulse with a duration of 5 seconds. During this interval, the output driver is disabled. The fault output is active low, and it’s driven by the CNT3/DLY3 output.
After 5 seconds, the output driver is enabled again. If the fan is still locked, the device will enter the fault state again.
The 3-input OR is used to disable the lock detection logic as described in the following section
Start-up timer
Since the fan can’t start spinning instantly due to its inertia, the lock detection logic might detect a false fault condition and disable the output driver prematurely. This block is used to bypass the lock detection logic during the start-up of the motor to avoid this unwanted condition.
Figure 11 The start-up timer block is used to bypass the lock detection logic during the motor’s start-up. Source: Renesas
The block uses the CNT2/DLY2 in one shot mode activated on the falling edge. The falling edge is generated either by the POR or by the “SHDN” signal. In the first case, a rising edge detector generates a short pulse triggered by POR, so the start-up signal is generated at power-on. A falling edge of the “SHDN” signal instead corresponds to all the cases in which the fan is being restarted.
When the falling edge is detected, the “STARTUP” output goes high for about 125 ms, forcing a logic 1 at the input of CNT1/DLY1 no matter what signal is coming from CCMP0 (see Figure 7). This allows engineers to disable the lock detection chain that is triggered by falling edges; the “STARTUP” signal could just generate a rising edge, but it will have no effect.
Minimum speed and stop threshold
The design allows engineers to set a minimum fan speed and a minimum temperature below which the fan is disabled.
Figure 12 This block sets a minimum fan speed and a minimum temperature below which the fan is disabled. Source: Renesas
For this purpose, two voltage comparators are used. The inputs of the comparators are connected to the VIN voltage, which controls the speed of the fan and is proportional to the sensed temperature.
Due to the direct proportionality between input voltage and speed, it’s possible to set the minimum fan speed by setting the voltage threshold on the comparator. When the input voltage goes below the threshold, the output of the comparator (MIN SPEED) goes low and, through the 2-bit LUT, forces high to “keep” input of the PWM macrocell. In this way, the output duty cycle can’t decrease any further as long as the input voltage is below the threshold, thus setting a minimum fan speed.
A similar concept is valid for the other comparator. In this case, the voltage threshold must correspond to the minimum temperature according to the temperature sensor. When the input voltage goes below the threshold, the output of the comparator (FAN STOP) goes low and disables the output driver, stopping the fan.
For both comparators, a 32-mV hysteresis is used.
Final implementation
Below is the graphical depiction of the proportionality between the input voltage and the output duty cycle.
Figure 13 In output waveform (C1), VIN ≈ 1 V (C2). Source: Renesas
Figure 14 In output waveform (C1), VIN ≈ 1.5 V (C2). Source: Renesas
Figure 15 In output waveform (C1), VIN ≈ 2.4 V (C2). Source: Renesas
Figure 16 Fan current (C1) and fault output (C2) are shown when the fan is forced to stop. Source: Renesas
Here is how the minimum temperature looks like when the fan is stopped and the input voltage goes below a minimum threshold.
Figure 17 Here is how the final results’ output waveform (C1) and input voltage (C2) look like. Source: Renesas
This article has shown how the high-voltage GreenPAK IC SLG47105 can be configured to implement a smart pulse width modulation (PWM) fan driver with minimal external components. The design is flexible and can be adapted to a wide variety of fans, thanks to the high-current capable integrated driver. The design also allows engineers to easily configure parameters, including PWM frequency, minimum speed and minimum temperature.
This article was originally published on Planet Analog.
Gabriele Mantovani is an electronics engineer.
