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Second-stage output filters are often used to attenuate the output voltage ripple of a switching power supply. They can also isolate one load circuit from another. In this power tip, I will describe the typical design criteria to meet a load transient specification.

The design example here is a negative-to-positive inverting buck-boost converter. **Figure 1** is a simplified schematic for a single-phase equivalent circuit. The 48-V/25-A negative-to-positive synchronous buck-boost reference design for power amplifiers from Texas Instruments includes a complete design and test report for a four-phase 1,200-W converter.

**Figure 1** The 300-W single-phase buck-boost equivalent circuit is used for simulation.

For this application, there is no hard specification for the output capacitor voltage ripple, but you need some reasonable attenuation due to the inherently large output ripple current. For the transient response, the typical design requirement calls for a 3% output voltage deviation given a 50% step in load current.

To meet the transient requirement, you will need to ensure that the impedance of the output filter is low enough and that the control-loop bandwidth is high enough to keep the output voltage within tolerance during a load current step.

For this application, the main objective is to minimize size and cost. The first step in this strategy is to use ceramic capacitors for the first stage, chosen for their root-mean-square (RMS) current rating. The inductor value needs to be high enough to reduce the ripple current, while keeping the second-order peaking to a reasonable value for stability. Choosing a second-stage aluminum polymer capacitor for transient holdup will provide enough resistance to dampen the filter, in parallel with a lower-value ceramic capacitor.

**Design method and calculations**

You’ll need to determine the RMS current in the output capacitors, the worst case being at the minimum input and maximum load. Using Power Stage Designer 4.0, the output capacitor ripple current is 7.5 A. This can also be approximated as Equation 1:

where D is the duty cycle given by D = V_{O} / (V_{O} + η · V_{IN}) and η is the efficiency.

Equation 2 expresses the ripple voltage on the first-stage ceramic capacitors as:

where the capacitor peak-to-peak ripple current is I_{PP} = I_{L} + ΔI_{L} / 2.

Choosing ceramic capacitors to handle the RMS current rating is easy, since 1206 or 1210 packages are rated from around 3 A to 6 A. You will need to be mindful of the ripple voltage, so let’s determine the required capacitance from that. Since the load transient target is 48V × 3% = 1.44V, let’s use it as the target for the first-stage ripple voltage. We find I_{PP} = 19.3 A in Power Stage Designer and solving Equation 2 for C = (19.3 A · 0.58 · 0.42) / (1.44V · 150 kHz) = 21.8 μF using five 4.7-µF, 100-V ceramic capacitors.

The next step is to determine the AC ripple current attenuation to find the inductor value. Since the first-stage ceramic capacitors have a triangular ripple voltage, Equation 3 gives the second-stage inductor ripple current as:

Using an attenuation factor of 20%, the inductor peak-to-peak ripple current is 19.3 A × 0.2 = 3.86 A. The inductor value is L = 1.44V / (8 · 3.86 A · 150 kHz) = 310 nH, so you can use a standard value of 330 nH.

**Figure 2** shows the ripple voltage and current waveforms.

**Figure 2** The second-stage filter simulation results show ripple voltage and current.

To meet the transient load requirement, first make sure that the total output capacitance is sufficient to hold up the output voltage based on the converter’s bandwidth. Second, make sure that the output impedance is low enough to keep the initial step within bounds.

To determine the output capacitance requirement, you need to know the estimated control-loop bandwidth. For a higher-power buck-boost converter, the right-half-plane zero of the power stage tends to be the limiting factor. The worst case occurs at a minimum input and a maximum load, and is found in the presentation in Reference 1 as ƒ_{RHPZ} = (R_{O} · (1 – D)^{2}) / (2 · π · L_{1} · D) = (7.68 Ω · 0.42^{2}) / (2 · π · 15 μH · 0.58) = 24 kHz.

Due to the inherent peaking of the second-stage filter, you need additional stability margin, so set your control-loop bandwidth to one-tenth of the right-half-plane zero so that f_{C} = 2.4 kHz. Using the paper in Reference 2, find C_{OUT} = I_{P} / (2 · π · ƒ_{C} · V_{P}), where I_{P} is the load current step and V_{P} is the allowable output voltage deviation. Identifying the load current from Figure 1 as 6.25 A, the required capacitance is C_{OUT} = (6.25 A · 0.5) / (2 · π · 2.4 kHz · 1.44V) = 72 μF.

A 100-μF aluminum polymer capacitor is selected, which has an equivalent series resistance of 24 mΩ and a 3-A RMS current rating. Adding two 4.7-μF ceramic capacitors in parallel provides some additional attenuation of the output ripple voltage.

Now compare the transient voltage caused by the filter impedance, considering the resonant frequency and damping. Given a fast load transient, the equivalent series resistance of the aluminum polymer capacitor determines the initial voltage deviation, found as V_{P(Rc)} = I_{P} · R_{C} = 3.125 A · 24 mΩ = 75 mV, which is well within the 3% limit.

The series equivalent capacitance for resonance is simply C_{s} = (C_{a} · C_{c}) / (C_{a} + C_{c}) = (20 μF · 100 μF) / (20 μF + 100 μF) = 16.7 μF.

The characteristic impedance of the second-stage filter is Z_{filter} = √ (L_{2} / C_{s}) = √ (330nH / 16.7 μF) = 140 mΩ.

The resonant frequency is ƒ_{res} = 1 / (2 · π · √ (L_{2} · C_{s}) = 1 / (2 · π · √ (330nH · 16.7 μF) = 68 kHz.

The ratio of the reactive to real impedance will determine the gain peaking as A_{VP} = 20 · log(140mΩ / 24 mΩ) = 15 dB.

For stability, you need to ensure that the peaking stays below unity gain in closed loop.

**Closing the feedback loop**

To close the control loop using a second-stage filter, there are two possible feedback points. One is at the converter before the second-stage filter and one is at the load side of the filter. Let’s determine the impedance at these points, corresponding to V_{a} and V_{o} in **Figure 3**. Consider the current-mode control power-stage output to be a current source for this analysis, and the load is a constant current.

**Figure 3** A second-stage filter can be used for impedance analysis.

The defining terms are Equations 4, 5, and 6:

Equation 7 expresses the impedance at V_{a} as:

Substituting for terms and simplifying, this becomes Equation 8:

Equation 9 expresses the impedance at V_{o} as:

Substituting for terms and simplifying, this becomes Equation 10:

From the equations, you can see that the denominators are identical. There is a dominant pole of the output capacitors and a complex conjugate pole of the second-stage inductor and series capacitors. **Figure 4** clearly shows the resonance of the complex conjugate pole with its peaking and associated phase shift.

The gain and phase of the impedance at V_{o} is as expected. There is an initial pole with a 90-degree phase shift, followed by the complex conjugate pole with a phase shift of 180 degrees. The impedance at V_{a} has a complex conjugate zero in the numerator. Since C_{c} is larger than C_{a}, this zero occurs at a lower frequency than the complex conjugate pole. The end result is a single pole, but with substantially higher peaking at resonance. The dotted-line graph shows the impedance with L_{2} = 0.

**Figure 4** Second-stage filter impedance demonstrates peaking and associated phase shift.

So where should you close the control loop? For a point-of-load converter with a large bulk output capacitance, you might consider closing it at V_{a} if the second-stage filters are branch taps for lower-current loads. In this case, V_{o} is the correct choice, since the corner frequency is well above the control-loop bandwidth.

You can see from the graph in **Figure 5** that the bandwidth is a bit over 2 kHz. Note the gain peaking from the second-stage filter. If the peaking crosses the unity-gain axis of 0 dB, the control loop could become unstable and oscillate at the resonant frequency.

**Figure 5** Potential instabilities can be identified and avoided through frequency response testing.

As expected, the transient voltage deviation is on target at 1.4V, as shown in **Figure 6**.

**Figure 6** Transient response measurement also helps identify acceptable voltage ranges.

The simulation plots are in agreement with the measured results from the test report. Since the final-stage capacitors are in parallel for the four-phase converter, interleaved cancellation significantly reduces the actual output voltage ripple.

*Robert Sheehan is a systems applications engineer, developing custom power solutions as part of the Power Design Services team at Texas Instruments.*

**References**

- “Switch-mode power converter compensation made easy,” Sheehan, R., and Diana, L., Texas Instruments Power Supply Design Seminar SEM2200, 2016-2017.
- “Frequency Compensation and Power Stage Design for Buck Converters to Meet Load Transient Specifications,” Bag, S., Mukhopadhyay, S., Samanta, S., Sheehan, R., and Roy, T., 2014 IEEE Applied Power Electronics Conference and Exhibition (APEC) 2014, 1024-1031.

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