Impact of embedded capacitance material on power integrity

Article By : Chang Fei Yee

This article discusses the benefits of applying embedded capacitance material (ECM) on PCB versus conventional FR4 dielectric material in terms of power integrity by analyzing the power distribution network (PDN) impedance, simultaneous switching noise (SSN) and jitter.

The transient current in IC interacts with power distribution network (PDN) impedance and switching noise is generated, as governed by Eq. (1). This noise is induced to the power rail and causes power integrity issue in terms of simultaneous switching noise (SSN) and jitter. Hence, it is necessary to keep the PDN impedance low.

Power rail noise = transient current x PDN impedance (1)

Referring to Fig. 1, impedance of all the PDN elements is lumped together and forms the impedance of a power rail. Voltage regulator module (VRM), bulk bypass and decoupling capacitor have resonant frequency below 500 MHz. Meanwhile, plane capacitance has resonant frequency above 500 MHz.


Fig. 1. Impedance profile of PDN elements on PCB (by B. Olney)

By applying embedded capacitance material (ECM) on PCB, lower PDN impedance at high frequency domain is achieved. With reference to Fig. 2, each ECM is ultra-thin (i.e., < 1 mil) and has very high dielectric constant or Dk (i.e., > 7) compared to conventional FR4 dielectric material. Hence, ECM is also known as ultra-thin high-K dielectric material.


Fig. 2. Properties of ECM (by Faradflex)

By applying ECM (i.e., thinner substrate and higher Dk) between power and ground (i.e., reference) planes in PCB, the plane capacitance is increased, as governed by Eq. (2), which in turn results in lower PDN impedance.

C = ε A / d (2)

C = plane capacitance

ε = dielectric property (Dk x εo)

A = overlapped region between power and ground

d = substrate thickness between power and ground

The PDN impedance, SSN and jitter for PCB stack-up with conventional FR4 material versus ECM is analyzed using network analyzer (VNA) and oscilloscope respectively.

Performance analysis on PCB with ECM versus FR4

The power rail of interest that supplies power to the LVDS data interface of processor is laid out on layer 6, with reference to ground plane on layer 5 in the PCB laminated with ECM and FR4 respectively. The PCBs with both substrate materials are mounted with the same quantity of bulk bypass and decoupling capacitors. Dielectric thickness between power and ground is 0.5 mil for stack-up with ECM versus 3.06 mil for stack-up with FR4. The ECM being used has Dk 9.5 versus Dk 3.81 in FR4.

The PDN impedance of the LVDS power rail on the prototype PCB is characterized by conducting 2-port S-parameter measurement using VNA with test setup depicted in Fig. 3. Firstly, SMA connectors are mounted on top and bottom of the PCB to probe a through-hole via connecting the power rail, with reference to ground. Subsequently, each port of VNA is hooked up to the SMA using RF cable. Before the RF cables are connected to the SMA on PCB, calibration must be performed to compensate the cable loss.


Fig. 3. Test setup for 2-port S-parameter measurement using VNA (by Keysight)

The measured S21 parameter is converted to PDN impedance using Eq. (3). Subsequently, the PDN impedance is plotted, as shown in Fig. 4. Across the wideband, the LVDS power rail on PCB with ECM (i.e., green curve) has lower impedance versus PCB with FR4 (i.e., red curve) except a narrowband that peaks at 70MHz with 1 ohm.

ZPDN = 25 x S21 (3)

ZPDN = PDN impedance


Fig. 4. PDN impedance plots for LVDS power rail on PCB with ECM versus FR4

The performance ECM versus FR4 is further verified by analyzing SSN using oscilloscope. The measured SSN in frequency domain for the power rail on PCB with ECM and FR4 are shown in Fig. 5. The LVDS interface is operating at 800Mbps, with Nyquist frequency 400MHz. Spectral analysis (i.e., FFT function in oscilloscope) is conducted for wideband up to 1GHz. The SSN power spectrum on PCB with ECM is lower versus FR4 in terms of dBm across the wideband except the narrowband range near 70 MHz, due to the higher PDN impedance at narrow band around 70MHz for ECM, shown in Fig. 4.

ECM vs FR4

Fig. 5. SSN for LVDS power rail with ECM (top plot) versus FR4 (bottom plot) in frequency domain

On the other hand, the measured SSN in time domain for LVDS power rail after AC coupling on PCB with ECM and FR4 are shown in Fig. 6a and 6b respectively. The power rail noise on PCB with ECM (i.e., 30mVpp) is lower versus FR4 (i.e., 48mVpp).


Fig. 6a. SSN for LVDS power rail with ECM in time domain


Fig. 6b. SSN for LVDS power rail with FR4 in time domain

Lastly, probing is conducted on LVDS data signal to generate eye diagram to compare the noise performance between ECM versus FR4, depicted in Fig. 7a and 7b respectively. The LVDS data operates at 800Mbps, with unit interval (UI) 1.25ns. LVDS data with ECM has 1.128ns eye width, or total jitter 122ps. Meanwhile, LVDS data with FR4 has 1.07ns eye width, or total jitter 180ps. Jitter experienced by LVDS data with FR4 is larger versus ECM, due to larger SSN contributed by higher wideband PDN impedance.

PCB with ECM

Fig. 7a. Eye diagram for LVDS data on PCB with ECM

PCB with FR4

Fig. 7b. Eye diagram for LVDS data on PCB with FR4


The study effort in this article proves that ECM outperforms conventional dielectric material in terms of PDN impedance, SSN and jitter. The SSN and jitter are reduced by 37.5% and 32% respectively when ECM is applied in PCB versus PCB with FR4.


[1] F.Carrio, V.Gonzalez and E.Sanchis, "Basic Concepts of Power Distribution Network Design for High Speed Transmission"

[2] B. Olney, "Power Distribution Network Planning"

[3] Faradflex high Dk material data sheet

[4] Evaluating DC-DC Converters and PDN with the E5061B LF-RF Network Analyzer, Keysight Technologies

[5] Ultra-low Impedance Measurements Using 2-Port Measurements, Keysight Technologies

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