# Implementing load-line control for a multi-phase buck converter

#### Article By : Marisol Cabrera and Tomas Hudson

A load-line control improves efficiency as well as power supply transient response while reducing minimum required bulk capacitor.

With the proliferation of 5G networks, cloud computing, Internet of Things (IoT) and virtualization, IT infrastructure is driving the demand for high-performance computing servers.

Each new server generation requires higher computing power and efficiency, while also increasing power requirements. One of the key aspects in ensuring that servers meet market demands is to understand the effect that the microprocessor’s power supply has on both the dynamic response and efficiency of the server as a whole. That enables engineers to configure the power supply for optimal performance.

Server applications are especially demanding when it comes to transient response requirements. In order to meet these requirements, designers can implement load-line control, which is sometimes also referred to as active voltage positioning (AVP).

Understanding DC load-line design

Load line (LL) control refers to a modification of the voltage control loop where the buck converter’s output voltage (VOUT) is adjustable based on the load current. In other words, VOUT is no longer constant for all load values, and instead changes according to the power demand. The adjusted output voltage can be calculated using Equation 1:

VOUT = VOUT(NOM) – IOUT × RLL            (1)

Where VOUT(NOM) is the maximum VOUT when there is no load connected to the power supply, IOUT is the load current, and RLL is the equivalent load-line impedance (in Ω).

Figure 1 shows how implementing load-line regulation degrades the DC load regulation (denoted with the blue line), causing VOUT to slope down as the current increases, compared to the traditional approach that fixes VOUT for all loads (denoted with the green line). Note that the voltage slope created by the load line must still be designed to meet the VOUT requirements for powering microprocessors. This means that VOUT must fall within specified voltage limits—VMAX and VMIN—for the entire output current range.

Figure 1 The graph shows VOUT with DC load line vs. the fixed VOUT method. Source: Monolithic Power Systems (MPS)

The main reason to implement load-line regulation is to lower the voltage when the load current is very large, and thereby reduce power consumption and dissipation loss. While this is a frequently discussed benefit, another advantage of implementing load-line control is how it improves the server’s dynamic response.

Power supplies in server applications often have to support large load transients. This is because power supplies in server applications must power loads such as storage devices and CPUs, whose power requirements vary according to the task(s) they are executing. For example, it’s not uncommon for a server power supply to deliver current steps well above 100 A.

Figure 2 shows a power supply before and after implementing the load line. Due to the current step, the power supply without a load line—denoted with the purple line—experiences large overshoots and undershoots during load transients. If these peaks exceed the maximum or minimum voltage limits, this can cause the load to break down and cease functioning. By gradually adjusting VOUT with the implementation of a load line—denoted with the blue line—these peaks can be eliminated and the transient response is improved.

Figure 2 The power supply comparison before and after implementing the load line highlights effects on transient response. Source: Monolithic Power Systems (MPS)

While load line improves server performance and efficiency, the load-line configuration must be very accurate, since the converter must always operate within the set voltage limits. Most communication standards specify ideal load-line values, but these values may need to be tweaked due to different board materials and layouts. Otherwise, the load line may push the voltage below the minimum requirements when operating at high power (Figure 3).

Figure 3 Here is a view of errors caused by suboptimal load-line configurations. Source: Monolithic Power Systems (MPS)

Reducing output capacitance with DC load line

To demonstrate the benefits of load line control, a general example was created with typical processor specifications for a power rail. The input voltage (VIN) was set to 12 V, the output current (ITDC) was 220 A, and the output voltage (VOUT) was 1.8 V—all of which are generic values for a voltage rail in server applications. Table 1 shows the specifications.

Table 1 Power rail specifications. Source: Monolithic Power Systems (MPS)

Table 2 shows the test conditions such as output capacitance (COUT), switching frequency (fSW), and the number of phases (NPHASE).

Table 2 Test parameters. Source: Monolithic Power Systems (MPS)

A dual-loop, digital, multi-phase controller—MP2965—was used to implement this example, since it supports load-line configuration and can be configured for up to 7-phase operation. The PMBus-configurable load line requires a droop resistor (RDROOP) to be connected between the VDIFF and VFB pins, as well as internal register configurations (Figure 4)

Figure 4 Here is how the controller-based load-line internal structure looks like. Source: Monolithic Power Systems (MPS)

First, a designer must establish the effect of the load line by observing the voltage regulation when the converter does not use a load line. A 160-A current step was applied to the MP2965 multi-phase controller to emulate a CPU load. Figure 5 shows the converter’s response without a DC load line. Note the large VOUT spikes that occur during the current transients. This means there is a voltage variation of 205 mV, which is barely inside the specifications shown in Table 1.

Figure 5 The converter response to a current step is without DC load line. Source: Monolithic Power Systems (MPS)

Using Equation 1, a load line of 0.67 mΩ was designed to meet the minimum VOUT specification, estimated with Equation 2.

VOUT = VID – IOUT × RLL → RLL = VOUT(NOM) – VOUT(MIN)/IOUT(MAX) = 108 mV/160 A = 0.675 mΩ           (2)

Figure 6 shows the resulting transient response after implementing a DC load line.

Figure 6 The converter response to a current step is with DC load line. Source: Monolithic Power Systems (MPS)

By implementing a DC load line, VOUT stays well within the voltage range specified in Table 1, with a voltage margin of about 50% of the permitted range. This increased voltage margin also means that certain design constraints can be loosened, such as the output capacitance, which is one of the key elements used to reduce the peaks in output voltage. As specified in Table 2, the voltage responses shown in Figure 5 and Figure 6 refer to a total output capacitance of 4.7 mF, comprised of 60 22-μF MLCC capacitors placed close to the CPU load, along with a few aluminum electrolytic capacitors.

The MLCC capacitors filter out the high-frequency components of the current transient response, whereas the aluminum electrolytic capacitors filter out the low-frequency components. These aluminum capacitors, called bulk capacitors, are specially designed with a very low equivalent series resistance (ESR), meaning that they are typically the most expensive capacitors in the circuit. As a result, having fewer bulk capacitors reduces the overall cost and BOM.

Since implementing the DC load line already reduces the transient peaks, bulk capacitance becomes less crucial for transient response and the bulk capacitor’s ESR requirements are also reduced. Therefore, some of the bulk capacitors can be removed without having a significant effect on the circuit’s transient response. Figure 7 shows the results after reducing the bulk capacitance by 50% (from 6 x 470 µF to 3 x 470 µF).

Figure 7 The converter response to current step is with DC load line and fewer bulk capacitors. Source: Monolithic Power Systems (MPS)

To increase the voltage margin for both positive and negative spikes, a 40-mV DC offset was added to VOUT. This places VOUT near the center of the voltage range defined by the specifications.

Although there are fewer bulk capacitors, there is no visible change in the power supply’s transient response. However, this still provides the advantage of reduced cost and board space.

An additional benefit of load line is the reduced CPU power dissipation. When VOUT is set to 1.8 V at 160 A, the load power is 288 W. By implementing the DC load line and decreasing VOUT to 1.725 at maximum current, the load power from Figure 7 is 276 W, which represents a net power saving of 12 W.

Benefits of load-line control

Server and computing applications require power supplies that can handle large, sudden shifts in current while meeting strict VOUT regulation requirements.

Using a digital controller to implement a PMBus-configurable load line, this article has demonstrated the load-line control benefits such as improved efficiency and improved power supply transient response performance. The article also explained how implementing a DC load line reduces the minimum required bulk capacitance, allowing designers to reduce overall cost and minimize board space while still meeting specifications for server applications.

This article was originally published on EDN.

Marisol Cabrera is senior applications engineer at Monolithic Power Systems.

Tomas Hudson is applications engineer at Monolithic Power Systems.