Is 5 nm testing the same or different?

Article By : Robert Ruiz

Production test at the bleeding edge of IC fab requires new approaches.

With every process node advance, new types of manufacturing defects manifest. These defects are especially prevalent during the early phase. For early adopters, silicon manufacturing tests must evolve to capture as many defects as possible. FinFETs, by nature of their different physical structure compared to planar transistors, come with new types of defects – primarily those that occur on their fins. What test methodologies and technologies must be applied to detect all manufacturing defects present in new process nodes such as 5 nm and beyond? If not captured at silicon test time, defects manifest as field failures, increasing costs and eroding profit margins. This article focuses on slack-based transition and cell-aware tests to improve the quality of silicon testing.

FinFET testing: Basics

Whereas leakage power and short-channel effects have plagued planar MOSFETs at advanced geometries, the FinFET enables higher drive current and ability to suppress off-state leakage current [2]. The FinFET sandwiches a nanometer-thin dielectric between a vertical fin and a gate that surrounds it on three sides to form a conducting channel (Figure 1a). Since the fin dimensions are fixed by the manufacturing process, the drive strength of a logic gate is increased discretely by increasing the number of fins that run parallel between a common source and drain (Figure 1b). For 5nm FinFET technologies and beyond, one major advance is gate-all-around (Figure 2) to improve performance variability and to scale the gate length.

Figure 1(a) Cross section of a FinFET. (b) FinFET with multiple fins connected in parallel to increase drive strength.

Figure 2  Gate-all-around FinFET

To detect manufacturing defects on these FinFETs, automatic test pattern generation (ATPG) tools target models of defects (known as “fault models”) and generate a test program. The test program is applied by a tester to the silicon, determining if each die passes (defect-free) or fails (defective). If a defect essentially causes a transistor to be stuck on or off, ATPG tools such as Synopsys TetraMAX II can target a test for the defect using the classical fault models — stuck-at, IDDQ, and bridging faults. Indeed, these fault models are the same type of fault models applicable to testing planar MOSFETs.

However, what about defects that are unique to FinFETs and correspond to abnormal behavior that is not stuck on/off? Table 1 below summarizes several types of physical defects that could occur only in FinFET devices, which process variations can lead to these defects and how they impact delay and leakage behavior in logic gates [3].

Resistive open on a fin

Let’s briefly examine one of these defects and their fault effects, specifically the defect that is a resistive open on a fin. Over-etching can cut into a fin, leading to a resistive open. Consider a CMOS inverter composed of multiple p-type fins, one of which has a resistive open on the drain (Figure 3).

Figure 3 (a)  Layout topology showing a resistive open on a fin of a p-type FinFET. (b) Transistor representation of a CMOS inverter with a resistive open affecting one of several p-type fins. (c) Fault-free and faulty behavior of the output signal.

If there is at least one p-type fin that is not completely severed, the gate still functions correctly but with lower drive strength that results in increased delay. The magnitude of this delay depends on the extent of the damage and the number of damaged fins. If the fin is completely severed, R approaches infinity and the extra delay is observed in the low-to-high transition at the inverter output. Additional delay would occur if there were other severed or partially-severed fins. To target defects causing signal transition delays, an “at-speed” test is required. These types of tests can be created by ATPG tools using transition delay, path delay, hold-time, and faults. The resulting tests can detect resistive opens if the total added delay is significant.

If, however, only one fin is partially severed, R can be much less than infinite but still exceed the resistivity of the defect-free case. In this scenario, only a relatively small extra delay is added. These small extra delays are examples of “small delay defects” that can lead to invalid responses when a design operates at the targeted frequency. Similar analysis of other fin defects, such as resistive shorts on fins and gate fin shorts, similarly show an impact on output response times. These types of defects are typically difficult to target with traditional transition delay tests since they are often incapable of detecting such defects using short combinational testing paths with a high amount of timing slack. On the other hand, slack-based transition delay tests, discussed in the next section, are capable and essential to covering small delay defects on fins.

Slack-based transition delay test

Transition delay fault test is an “at-speed” test, meaning that the test program is applied at fast speed. Standard transition fault tests are effective detecting defects associated with nominal delays, but they do not explicitly target delay faults along their minimum-slack paths. As a result, they are not effective detecting the small delay defects that can occur in FinFETs and advanced processes. In contrast, slack-based transition delay tests efficiently cover defects that create even miniscule delays. This is possible because faults are targeted along minimum-slack paths, causing the actual signal to fail in propagating within its allotted time. One example of a means to generate this test is leveraging static timing analysis providing the slack information from Synopsys’ PrimeTime to guide the pattern generation of TetraMAX II ATPG.

As an example of increased detection of FinFET fin faults with slack-based transition delay tests, consider the circuit in Figure 4. This circuit shows two possible detection paths for a delay fault at the output of a FinFET NAND gate. Path A is the fault’s minimum-slack path meaning that the incorrect value with be detected if the signal is only slightly slowed down. Standard transition test ATPG most likely would not cover the small delay defect because it would target the delay fault along Path B, the easiest-to-detect path. Because Path A is the minimum-slack path, it is the preferred target transition path for a delay fault.

Figure 4 Slack-based transition test detects a small delay defect in the FinFET NAND gate

Cell-aware ATPG

In addition, cell-aware fault tests can be used to target transistor-level defects within library cells, such as open drains and other defects. The type of defects might not be covered by standard ATPG, which only targets faults on pins of cells. Cell-aware ATPG is described in more detail below.

Cell-aware test is well-suited for cells with logic optimized to implement more complex Boolean functions, such as the conditional carry gate shown in Figure 5.

Figure 5  Conditional carry gate

To perform cell-aware tests, the ATPG tool must be guided by cell test models. The basic idea behind the models is illustrated in Figure 6, which shows how resistors can be connected to transistors and assigned values that approximate the behavior of various physical defect types, such as opens on drains, source-drain shorts, etc. Inserting a parameterized resistor into a circuit netlist and performing a transient analysis allows one to compare good versus faulty behavior at the outputs. The simulations need to be accurate enough to predict faulty behavior observable as stuck-at-1/0 or added delay to the output transitions.

Figure 6  Resistors connected to transistors and assigned values that approximate the behavior of physical defect types.

The cell test model accessed by ATPG includes a two-cycle table used for transition delay testing. The table contains the input conditions required to target all the specified defects and, for each input condition, the output good machine values and defects covered. Table 2 is a conceptual representation of the cell test model of the example cell. If a defect Dx is detected by a given input condition, the corresponding column displays a Boolean value 1, otherwise 0. In the table entries, a 1 or 0 represents the same constant value in both cycles, an “R” symbol represents a rising transition, and an “F” symbol represents a falling transition.

Table 2  Representation of the cell test model of the example cell.

Conclusion

High defect coverage is essential for emerging process nodes, and can be achieved at FinFET nodes, including 5 nm, by applying multiple tests. In addition to stuck-at and standard transition delay faults, ATPG tools must target slack-based transition and cell-aware faults. Unlike planar MOSFET gates, FinFET gates utilize multiple fins to increase drive strength. Slack-based transition tests can effectively detect small delays that could arise when some of the fins are damaged. Finally, to further improve defect coverage to virtually-zero DPPM, a cell-aware test solution generates patterns that target defects inside cells.

Related articles:

• Characterizing mixed-signal ICs for production
• Low-voltage tests uncover low-temperature IC problems
• Rethink fault models for submicron-IC test

 —Robert Ruiz is the Senior Product Marketing Manager for the test automation products at Synopsys, Inc. His background includes 17 years in advanced design-for-test methodologies as well as several years as an ASIC designer. Robert has a BSEE from Stanford University.

References

[1] Appello, D.; Mattiuzzo, R.; Allsup, C., “Small Delay Defect Testing,” EDN, June 2009.

[2] Biddle, A.; Chen, J., “White Paper: FinFET Technology–Understanding and Productizing a New Transistor,” April 2013, Synopsys, Inc.

[?] Semiconductor Engineering What Transistors Will Look Like At 5nm As finFETs run out of steam after 7nm, what comes next? The debate is just beginning.August 18th, 2016 – By: Mark LaPedus

[3] Liu, Y.; Xu, Q., “On Modeling Faults in FinFET Logic Circuits,” Proc. International Test Conference, 2012, pp. 1–9.

[4] Kapur, R.; Zejda, J.; Williams, T.W., “Fundamentals of Timing Information for Test: How Simple Can We Get?” Proc. International Test Conference, 2007, pp. 1–7.

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