Veteran engineer Lee Ritchey casts doubt on the viability of PAM4 as the high data rate solution.
At DesignCon 2018's "Case of the Closed Eye" panel, I stood before you and declared "NRZ is done. It's over. Move on." Not everyone agrees.
In our inexorable march to ever higher electrical data rates, now 56 Gb/s with 112 Gb/s coming soon, many of us have been smug in our belief that, by trading a factor of two in bandwidth for 9.5+ dB loss in signal-to-noise ratio (SNR) and paying the difference in forward error correction (FEC), we can encode two bits per symbol with 4-level pulse amplitude modulation (PAM4), leave the clock rate unchanged, and double the data rate. Voilà, nothing to it (Figure 1).
Figure 1. PAM4 signals encode two bits in each eye diagram, twice the data rate of NRZ at the same clock rate.
I’ve been told that it can be valuable, now and then, to ponder the obvious question: Is this really necessary?
I sought the wisdom of the vocal PCB designer Lee Ritchey, the veteran engineer who was once described as “the high-speed design ratchet man.” He said, “I’ve seen PAM4 represented as the silver bullet several times before only to be rejected as too complex. I think that is true now as well and see no reason this will change.” With three eye diagrams, 12 separate rise and fall times, inter-eye skew and compression, plus the previously mentioned 9.5+ dB drop in SNR, not to mention the increased cost, footprint, and power demanded by FEC or the hassle of trying to predict BERs (bit error ratios) from symbol-error ratios (SERs) infected by inter-symbol interference (ISI), there’s no question that PAM4 is a complicated beast. Still, it has been adopted by more than 50 Gigabit Ethernet standards like IEEE 802.3bs and 802.3cd and OIF-CEI 4.0 (Optical Internetworking Forum-Common Electrical Interface) for lane rates over 50 Gb/s.
With insertion loss at the Nyquist frequency that exceeds 30 dB, ISI caused by the channel’s frequency response and reflections, we thought that good old baseband NRZ (non-return to zero, or PAM2) was obsolete for distances more than an inch or so. Figure 2 shows a channel response that for a clock frequency of 28 GHz (needed for 56 Gb/b NRZ), insertion loss is far too great.
Figure 2. Frequency response of a channel that’s clearly inadequate for data rates of 56 Gb/s (Source: Ransom’s Notes).
Ritchey burst that bubble too: “We have solved the loss and speed problems with improved dielectrics and silicon. Right now, loss is not the overriding issue. Glass weave induced skew is a much bigger problem.” Differential skew misaligns the n and p signals. Misaligned differential signals have common-mode noise, which reduces horizontal eye opening and exacerbates EMI and crosstalk. “We need some standards on how glass fibers are woven to make them more uniform and we are not getting it…I don’t see ISI come up in any of my discussions with clients at this point.”
If not PAM4, then what?
“We have already extended NRZ to 56 Gb/s in hardware that is in prototype and will ship next year,” Ritchey said. “This allows us to have two lanes going to a fiber channel to get 100 Gb/s on the fiber, which I think is about the limit of the optical parts. That should hold us for quite a while.”
Terence Regan, a Field Application Engineer from Amphenol, corroborated Ritchey’s claim in an interview by Eric Bogatin: “PCB technologies can absolutely support 56 Gb/s NRZ signaling and beyond. It’s cost effective, its proven technology and it’s been with us a long time, and will continue to be. We have a lot of life left to support the electronics industry.”
How will we get to 100+ Gb/s per lane?
“I suspect that losses in the paths will set our limits,” said Ritchey, “but PAM4 won’t solve this problem. It is just too complex and does not have adequate noise margin. We have about hit the limits on what we can do to dielectrics to reduce loss. A loss tangent of .002 is already common and you can’t go much below this unless you switch to air!”
“I don’t know of anything right now other than NRZ,” he continued. “I don’t see silicon that will let us have 100 Gb/s channels. That implies rise times on the order of 2 ps. The rise times required by the silicon are going to have to be hellish. A single bit will only be 10 ps.”
That said, I didn’t get the impression that Ritchey anticipated the need for drastic solutions like integrated photonics. I asked if he had any idea what innovations—like advanced PCB materials and equalization schemes that play nicely with FEC—would be required to get us there.
“I do expect that we will continue to see more clever things devised in the way of error correction and compensation. Don’t know what at this point. If I have learned anything in this industry it is: If there is enough money in it, someone will figure out a way.”
— Ransom Stephens is a technologist, science writer, novelist, and Raiders fan.