JEDEC’s Signaling Protocol Makes Flash Reset Simpler
Article By : Paul Hill
The industry standards body JEDEC has defined a serial reset protocol that avoids the need for a dedicated reset pin.
Today’s embedded systems, such as smart devices and endpoints in the IoT, often require instant-on capability while combining high performance with low power consumption. All electronic systems should also include the ability to recover from conditions induced by transient faults. Such faults are often closely dependent on signal integrity, which is something that is made more challenging in today’s high-speed designs.
Recovering from a runtime fault typically requires being able to instigate a controlled reset to all or parts of the system. In extreme circumstances, and where provision for a soft reset hasn’t been made, this can dictate the need to power-cycle a device. For IoT endpoints in remote locations, this can be problematic and expensive, thereby providing just one example of how important reset functions have become in embedded design.
The Serial Peripheral Interface (SPI) is widely used to connect peripherals and memory to a microcontroller or processor in embedded systems. Resetting serial flash memory is an important part of initialization or recovery. To enable SPI memories to be more easily reset by the host processor, the industry standards body JEDEC has defined a serial reset protocol that avoids the need for a dedicated reset pin. This article describes the reset protocol and its use, with particular reference to expanded SPI (xSPI) and executing code from serial non-volatile memory.
The role of SPI flash
The main advantage of a serial interface with respect to a parallel bus is the reduced number of signals required. Fewer signals and I/O pins reduces component cost and power consumption in most cases, as the power required to drive signals off-chip can be a significant contributor to the total power consumption.
The original SPI specification had four signals: a serial clock (SCLK) to synchronize data transfers; one or more chip selects (SS) to enable multiple targets to be addressed, and two data signals (MOSI and MISO) to transfer data in each direction. The standard has been extended in various ways to support higher performance, which now includes the ability to perform a soft reset over the SPI interface.
Serial Peripheral Interface (SPI)
(Source: Adesto Technologies)
To increase bandwidth, the SPI interface has evolved and developed, and variants now include dual SPI, which uses both data pins in a half-duplex configuration to send two bits per clock cycle, and quad and octal SPI, which add more data lines to transfer a larger number of bits per clock cycle. In addition, both of these can be used in double data rate (DDR) mode, which transfers data on both clock edges.
Quad and octal SPI interfaces are defined by the JEDEC expanded SPI (xSPI) standard, JESD251, which provides hardware guidelines to enable trouble-free integration of high-throughput xSPI devices in systems.
More recently, JEDEC has also defined and released a standard that provisions for resetting a device over the serial interface. This reset protocol, defined in JEDEC standard JESD252, removes the need for a dedicated reset pin in serial flash.
The standard defines the specific sequence that the chip select, clock, and input data signals need to follow in order to cause the device to perform a hardware reset. This pattern is used so that spurious transitions caused by noise on the serial data line don’t lead to an accidental reset. During a reset, the clock signal is held low, further ensuring that the pin transitions aren’t interpreted as a data transfer, while the chip-select pin is used to ensure that only a specific device is reset.
Reset protocol
(Source: Adesto Technologies)
SPI flash memory is widely used in embedded products, particularly for code. This makes it critical to overall functionality, and so it is essential to maintain reliable operation, including the ability to issue a reset if necessary.
Using reset for initialization and recovery
Systems generally use a reset function at power-up to ensure that all parts of the system start in a known state. Reset can also be used to recover from serious faults that may be caused by hardware problems during runtime, which include signal integrity and timing problems, electromagnetic interference, or random memory corruption caused by background radiation (see also “Mitigating Metastability”). Software bugs can also cause a program to crash and become unresponsive.
These occasional errors may be an inconvenience only for consumers, but they can be a serious problem for the IoT, in which thousands of nodes need to have high levels of availability. Increasingly, these devices may not be readily accessible for manual reset or power cycling. Embedded systems will typically use watchdog timers and other self-test mechanisms to detect failures and take corrective action. This may mean performing a “soft” reset wherein only the necessary subsystems are reset under the control of the processor.
The SPI interface is stateful. After receiving a command, for example, the flash memory will be expecting a certain number of address or data transfers. Any errors causing loss of synchronization between the host and the memory will result in unpredictable behavior. To recover from this, the host needs to be able to reset the serial memory to a known state by performing a soft reset. Such resets help maintain a stable system and are conducted without any outward indication of fault. As such, they can now be considered a standard feature of embedded system operation.
While some serial flash memories may have a dedicated reset pin, others use multiplexing in order to reduce pin count, in which case the reset pin will also be an I/O pin and, in some cases, the manufacturer may not provide a reset at all. Even if a reset pin is available, it may not be practical to dedicate an output from the microcontroller to control it. The JESD252 specification has been developed so that the serial flash memory device can still support a reset function without requiring a dedicated or physical reset pin. In addition to error recovery, the serial reset mechanism can be used at startup to ensure that serial memory is correctly initiated after power supplies have stabilized.
Execute-in-place
Traditional serial flash connects through a low-speed SPI, which means that if these devices are used to store program memory, the processor must first copy the code into on-chip SRAM prior to execution. Execute-in-place, or XiP, is serial flash memory that removes this requirement by offering a faster and wider interface. In turn, this reduces the need for on-chip SRAM and can subsequently allow a price reduction in the host microcontroller or processor.
Adesto’s EcoXiP features an octal SPI interface to deliver high performance with significantly lower power consumption compared to other octal devices and with much higher performance than quad-SPI memories.
Execution modes
(Source: Adesto Technologies)
For modern embedded devices, XiP is a valuable development, not least because on-chip flash memory is expensive and limited in size. Microcontrollers typically have a maximum of 1 MB of internal flash, but modern IoT nodes often need much more code space for features such as communication stacks, wireless interfaces, audio processing, machine vision, and application software. Using XiP with external flash enables much larger code storage. It also improves startup time by eliminating the code transfer stage.
The use of XiP leaves SRAM free for data storage rather than code, which reduces the amount of SRAM required. This can lower system cost by eliminating the need for external SRAM or allowing a microcontroller with less on-chip SRAM to be used. While NOR flash allows random access, the microcontroller needs to map the serial interface into its own memory space, so it is seen as just another area of memory and can therefore support XiP. To further improve performance, EcoXiP is optimized for code execution.
Standard SPI interfaces are designed for random accesses; each read consists of a command, an address, and the returned data. After the data is returned, another request can be made. However, instructions are often fetched from consecutive addresses. The EcoXiP interface exploits this by providing sequential bytes for each read request until a command with a new address is sent. This can double the bus throughput by removing the latency of sending a new address for each fetch. EcoXiP can deliver instructions at a sustained rate of 156 MB/s (266 MB/s peak).
Another problem with traditional NOR flash is that writes are orders of magnitude slower than reads. This means that data cannot be written to the flash while code is being executed from it because doing so would have a major performance impact. EcoXiP supports concurrent reads and writes by flexibly partitioning the memory into independent banks. This makes it possible to use XiP for code execution while, at the same time, saving data to the memory and performing over-the-air (OTA) updates.
Support for JEDEC standards, including remote reset, makes it simpler for the industry to adopt serial flash memory with XiP.
Conclusion
Being able to reset serial flash under the control of the host processor is an important requirement for embedded systems. The JEDEC JESD252 serial reset protocol enables this without the need for a reset pin on the memory or dedicated signal from a microcontroller or host processor.
Although the use of serial reset and XiP impacts design on both the host and the memory, a growing number of microcontrollers are adding support for these standards. Adesto was the first manufacturer to ship serial NOR flash that could support the serial flash reset signaling protocol and the xSPI standards. EcoXiP provides the required execution performance while reducing system power consumption and system cost. It also implements the standard for serial flash discovery and has other features for improved power efficiency and security.
Through these technologies, embedded engineers are better prepared to meet the challenges they face in developing products targeting the IoT.